Semiconductor memory device with error correcting circuit

Details Semiconductor memory device with error correcting circuit Semiconductor memory device with error correcting circuit

1987-03-17

1988-08-23

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Data refresh

365201, 365200, 371 13, 371 38, G11C 700, G11C 2900, G06F 1100, G06F 1110

Patent

active

047665734

ABSTRACT:
A semiconductor memory includes a plurality of cell blocks, a refresh control circuit which sequentially refreshes a plurality of the cell blocks, an access control circuit which accesses a plurality of the cell blocks, and an ECC circuit which is provided in a data path between the access control circuit and the plurality of cell blocks, so that the data which is input from and output to the access control circuit is converted to a predetermined bit converted data (so called code) by the ECC circuit and is stored in the plurality of cell blocks. Accordingly, when the access control circuit accesses the plurality of cell blocks, if the access cannot be carried out for specified cell block which is in a refresh state (that is, a correct data (code) cannot be written to or read from the cell block in a refresh state) the data in the access control circuit side can be reproduced as correct data by the ECC circuit. Therefore, viewed from the external, a predetermined access can be carried out without being affected by the refresh state.

REFERENCES:
patent: 3810129 (1974-05-01), Behman et al.
patent: 4106108 (1978-08-01), Cislaghi et al.
patent: 4112513 (1978-09-01), Elsner
patent: 4506362 (1985-03-01), Morley
patent: 4542454 (1985-09-01), Brcich et al.

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