Semiconductor memory device with enhanced reliability

Static information storage and retrieval – Read/write circuit – Testing

Reexamination Certificate

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Details

C365S225700

Reexamination Certificate

active

06781900

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device with enhanced reliability.
2. Description of the Background Art
FIG. 15
is a schematic block diagram showing a configuration of a prior art semiconductor memory device
502
.
In
FIG. 15
, there is shown, for simplification of description, a configuration including normal memory cells arranged in a matrix of 256 rows and 256 columns and in addition, one redundant memory cell column for improving a yield. In reality, however, normal cells are arranged in a matrix of a more number of rows and a more number of columns and furthermore, a plural number of columns of redundant memory cells are also provided in more of cases. Moreover, while in
FIG. 15
, one input/output terminal is shown, there is actually provided a configuration adapted to 4, 8 or 16 input/output terminals.
Referring to
FIG. 15
, semiconductor memory device
502
includes: a memory cell array
16
having plural memory cells MC arranged in a matrix; and a control circuit
508
receiving an address signal ADD, a clock signal CLK, control signals /RAS, /CAS, /WE, /CS and /CKE to output internal control signals CDE, CADE, a column address CA
0
to CA
7
, a row address RA
0
to RA
7
, a reset signal &phgr;
1
and a test signal TEST. Control circuit
508
includes a mode register
509
holding an operating mode of semiconductor memory device
502
.
Memory cell array
16
includes: memory cells MC arranged in a matrix, word lines WL
0
to WL
255
provided correspondingly to respective rows of memory cells MC; and bit line pairs BLP
0
to BLP
255
provided correspondingly to respective columns of memory cells MC.
Semiconductor memory device
502
further includes: an X decoder
10
decoding row address RA
0
to RA
7
given from control circuit
508
to selectively drive word lines WL
0
to WL
255
. X decoder
10
includes word drivers each driving a row (a word line) in,memory cell array
16
designated by an internal address to a selected state.
Semiconductor memory device
502
further includes: a program circuit
524
receiving reset signal &phgr;
1
corresponding to an address signal to output signals FCA and /FCA; a comparator
526
comparing column address CA
0
to CA
7
and signals FCA and /FCA with each other to output a signal SCE; a Y decoder
12
activated in response to control signal CDE and signal SCE to decode column address CA
0
to CA
7
and to select one of column select lines CSL
0
to CSL
255
; and a spare Y decoder
28
selecting a spare column select line SCSL in response to signal SCE.
Semiconductor memory device
502
further includes: a multiplexer
18
selecting a bit line designated by column select lines CSL
0
to CSL
255
and spare column select line SCSL for supplying/receiving data to/from outside; an input circuit
22
receiving a signal DQ given from a terminal to transmit signal DQ to multiplexer
18
; and an output circuit
520
outputting data read out from memory cell array
16
through multiplexer
18
to a terminal as signal DQ.
Next, description will be given of an outline of operation thereof.
In a case where a defective memory cell is to be accessed among normal memory cells, a redundant memory cell is accessed instead.
X decoder
10
selects one row among 256 rows according to address signal of 8 bits. Y decoder
12
selects one column among 256 columns according to address signal CA
0
to CA
7
of 8 bits. A defective column address is programmed in program circuit
524
. Comparator
526
compares an inputted address signal and a programmed defective column address with each other. If the inputted address signal coincide with the defective column address, signal SCE assumes H level to cause Y decoder
12
to be non-operable and spare Y decoder
28
activates spare column select line SCSL.
On the other hand, if the inputted address signals do not coincide with the defective column address, Y decoder
12
selects a column according to address signal CA
0
to CA
7
.
FIG. 16
is a circuit diagram showing a configuration of a portion corresponding to one bit of program circuit
524
.
Referring to
FIG. 16
, program circuit
524
includes: a fuse element
530
one end of which is coupled to power supply potential; a P-channel MOS transistor
532
the source of which is connected to the other end of fuse element
530
, and receiving reset signal &phgr;l at the gate thereof; an N-channel MOS transistor
534
connected between the drain of P-channel MOS transistor
532
and ground node and receiving reset signal &phgr;
1
at the gate thereof; an inverter
536
having an input connected to the drain of P-channel of MOS transistor
532
and outputting signal FCA; and an inverter
538
feeding back an output of inverter
536
to the input thereof.
When reset signal &phgr;
1
assumes H level, signal FCA is set to H level.
When reset signal &phgr;
1
assumes L level, signal FCA stays at H level as is if fuse element is disconnected while assuming L level unless fuse element
530
is disconnected. Accordingly, fuse element
530
has only to be disconnected in order to set signal FCA to H level.
FIG. 17
is a view for describing a shape of a fuse element.
Referring to
FIG. 17
, fuse elements F
1
to F
3
are made from an aluminum interconnection layer or a polysilicon layer. By irradiating a fuse element F
2
with a laser beam in a circle written with a broken line in the figure, the fuse element F
2
can be selectively blown.
In a case where a pitch d of fuses is reduced in order to shrink a chip size of a semiconductor memory device, however, requirements arise that a spot diameter of a laser beam is decreased or a strength of the laser beam is reduced in order to prevent blowing as far as adjacent fuses F
1
and F
3
from occurring.
With a smaller spot diameter of a laser beam or a reduced strength of a laser beam, a possibility occurs that fuse element F
2
is not completely disconnected even when fuse element F
2
is irradiated with the laser beam for programming fuse elements such that signal FCA is set to H level.
If a defect address is not correctly programmed, a semiconductor memory device does not operate normally, so improvement on yield is not realized even if saving is specially performed using a redundant memory cell. Especially, in a case where a fuse element is not completely disconnected to leave disconnected part thereof behind such that signal FCA shows an intermediate logical level between H level and L level, even if a semiconductor memory device with such a fuse element therein assumes a desired H level of signal FCA in a shipping test to then, operate normally, there is a possibility that signal FCA shows L level at a later chance, in which case there occurs a fear of malfunction of the semiconductor memory device since no replacement with a spare column has been implemented normally.
Accordingly, there has been a problem that, in actuality, a fuse pitch d of
FIG. 17
cannot be narrower, resulting in an increase in size of a semiconductor memory device.
SUMMARY OF THE INVENTION
It is an object of the resent invention to provide a semiconductor memory device with enhanced reliability, capable of detecting even incomplete disconnection with certainty in a case where a fuse element is not completely disconnected.
The present invention, in summary, is a semiconductor memory device having a normal mode and a test mode as operating modes and includes: a normal memory cell group; a redundant memory cell group; a program circuit; and a detection circuit.
A portion in the normal memory cell group where access is made is designated by an address signal. The redundant memory cell group is used as a substitution for a portion of the normal memory cell group when the portion of the normal memory cell group is defective. The program circuit holds information designating the defective portion in a non-volatile manner, and performs determination on whether or not an address signal designates the defective portio

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