Semiconductor memory device with electrically programmable redun

Details Semiconductor memory device with electrically programmable redun Semiconductor memory device with electrically programmable redun

1997-02-28

1999-08-03

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 36523006, G11C 700

Patent

active

059333766

ABSTRACT:
An integrated circuit having a memory which includes an array of data storage cells is provided with a redundant array and a signal-directing circuit. A row or column signal for a defective cell, if present, as well as each successively higher row or column signal, is directed to sequentially higher address locations in the array to thereby avoid the defective cell address location. The last row or column signal is directed to the address location of the redundant array. A fuse is preferably associated with each row or column signal which may be selectively melted to direct the row or column signals. The array can be logically divided into subarrays each having an associated redundant array so that defects in each subarray can be accommodated.

REFERENCES:
patent: 5586075 (1996-12-01), Miwa
patent: 5596542 (1997-01-01), Sugibayashi et al.
patent: 5610865 (1997-03-01), Shin et al.
patent: 5617364 (1997-04-01), Hatakeyama
patent: 5696723 (1997-12-01), Tukahara
patent: 5703817 (1997-12-01), Shiratake et al.
patent: 5708612 (1998-01-01), Abe

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