Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-02-06
2004-03-16
Auduong, Gene (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S149000, C365S154000
Reexamination Certificate
active
06707730
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device in which defect cells are replaced by redundancy cells.
2. Description of the Related Art
In semiconductor memory devices, a defect cell is replaced by a redundancy cell provided as a backup, and an access to the address of the defect cell is redirected as an access to the redundancy cell, thereby using the address of the defect cell as a valid address. For this purpose, generally, a whole row (i.e., word line) or a whole column (i.e., column line or data line) including a defect bit is replaced by a backup redundancy row or a backup redundancy column. Such replacement by the unit of one row or one column is an effective measure if a short-circuit or a severance of a damaged wire occurs with respect to a word line, a column line, a data line, etc. In the case of random defects that take place on a bit-by-bit basis, such replacement is not effective since the whole line may possibly be replaced for a single defective bit.
Against this background, Japanese Patent Laid-open Applications No. 1-303699 and No. 6-20494 each disclose a device in which a defective bit is specified as an intersection between a row and a column, and is matched against a redundancy bit on a bit-by-bit basis that is provided in a backup row or a backup column.
The degree of a random defect may not reach the level of a complete operational failure, and may be at such a level that the data retention time of a cell is shorter than a refresh interval that is set relatively long for the purpose of satisfying the demand for low power consumption. Such a cell is also treated as a defective bit. The data retention time of DRAM cells varies within a chip and exhibits a variation. When a cell of a short data retention time is replaced by a redundancy cell, therefore, the redundancy cell itself may be a defective cell having a short data retention time. In such a case, the redundancy technique of Japanese Patent Laid-open Applications No. 1-303699 and No. 6-20494 may not be as effective as to meet expectations.
Japanese Patent Laid-open Applications No. 64-59700 and No. 6-269299 each disclose a configuration in which an SRAM cell is used as a redundancy cell for bit-based redundancy processing. This makes it possible to avoid a replacement by a defect cell having a short data retention time.
The technology disclosed in Japanese Patent Laid-open Application No. 64-59700 uses a content addressable memory (CAM) or a circuitry comprised of a memory means and exclusive-OR gates as a means to detect a memory access to a defect address, and provides an address selection mechanism that is separate from that of a DRAM memory array. This makes it possible to redirect an access as an access to a redundancy bit while maintaining the access to the DRAM memory array as a valid access, thereby making it easier to control the timing of the DRAM. However, since the content addressable memory is comprised of logic gates and memory cells, an attempt to increase replaceable bits results in an increasingly complex circuit configuration and an increased circuit size.
In the configurations disclosed by Japanese Patent Laid-open Applications No. 64-59700 and No. 6-269299, a main memory and a backup memory are provided as separate units, and a selecting mechanism for accessing the main memory and an associated driver circuit are separately provided from a selecting mechanism for accessing the backup memory and an associated driver circuit. These circuitries are driven simultaneously, and a selection is made between the data of one of the circuitries and the data of the other. In this configuration, the main memory and the backup memory are provided with the respective circuitries as separate units, resulting in undesirable increases of chip size and power consumption.
Accordingly, there is a need for a semiconductor memory device that can cope with a single bit defect efficiently without an increase in chip size and power consumption.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a semiconductor memory device that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor memory device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a semiconductor memory device according to the present invention includes a data buffer for inputting/outputting data from/to an exterior of the device, a plurality of DRAM cell array blocks, an SRAM redundancy cell which is situated around each of the plurality of DRAM cell array blocks, a fuse circuit which stores therein an address of a defect memory cell in the DRAM cell array blocks, a comparison circuit which compares an input address with the address stored in the fuse circuit, and an I/O bus which couple the SRAM redundancy cell to the data buffer in response to an address match found by the comparison circuit.
In the invention described above, all bits of address signals (i.e., a row address, a block address, and a column address) are compared with the address of a defect memory cell to determine whether redundancy processing is necessary. In the case of redundancy processing being necessary, a data write/read operation is performed with respect to the SRAM redundancy cell. According to one aspect of the present invention, all the bits of the input address are compared with the address of a defect memory cell, thereby determining whether to select a routine column line or to select a redundancy column line. In the case of redundancy processing being performed, the selective activation of a redundancy column line and a block line achieves a data write/read operation with respect to the SRAM redundancy cell. This makes it possible to replace a memory cell with a redundancy memory cell on a bit-by-bit basis, and attains reliable redundancy processing based on the use of SRAM cells. Further, there is no need to provide an address selection circuit and a data access circuit dedicated for SRAM cells in addition to circuitry for DRAM memory cells, so that an efficient use of the chip area is achieved, and an increase in power consumption is prevented.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.
REFERENCES:
patent: 6563749 (2003-05-01), Ferrant
Matsumiya Masato
Mori Kaoru
Arent Fox Kintner Plotkin & Kahn
Auduong Gene
Fujitsu Limited
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