Semiconductor memory device with dual selection circuitry includ

Details Semiconductor memory device with dual selection circuitry includ Semiconductor memory device with dual selection circuitry includ

1989-10-31

1990-10-02

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Semiconductive

36518901, 365190, 36523003, 365203, 365204, G11C 700, G11C 11407, G11C 11408

Patent

active

049611640

ABSTRACT:
A semiconductor memory device is provided which includes a plurality of memory arrays each including main word lines, sub word lines to which a plurality of memory cells are connected, and a decoder which selectively connects the sub word lines to the main word lines. The main word lines are relatively short, since they are isolated electrically between memory arrays, and their resistance can thus be relatively low. The main word lines are not directly connected with a plurality of memory cells, and this results in a smaller capacitance coupled to the main word lines than is customarily the case. Consequently, the semiconductor memory device can have an enhanced operating speed.

REFERENCES:
patent: 4635233 (1987-01-01), Matsumoto et al.
patent: 4656614 (1987-04-01), Suzuki
patent: 4675845 (1987-06-01), Itoh et al.
patent: 4713796 (1987-12-01), Ogiue et al.
patent: 4734888 (1988-03-01), Tielert
patent: 4773049 (1988-09-01), Takemae
IEEE Journal of Solid-State Circuits, vol. SC-18, No. 5, Oct. 1983, "A Divided Word Line Structure in the Static RAM and its Application to a 64K Full CMOS RAM".

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