Semiconductor memory device with dual port memory cells

Details Semiconductor memory device with dual port memory cells Semiconductor memory device with dual port memory cells

2002-06-25

2004-08-24

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Addressing

Multiple port access

C365S154000

Reexamination Certificate

active

06781917

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device composed of dual port memory cells containing two ports for one memory cell.
2. Description of Related Art
First, an explanation on a single port memory cell will be given.
FIG. 11
is a block diagram to illustrate a conventional two-word configuration SRAM provided with two data input/output terminals. In the drawing, reference marks X
0
to X
8
designate a row address signal input terminal, Y
0
to Y
8
denote a column address signal input terminal, Z
0
denotes a block address signal input terminal, reference numerals
101
,
102
denote memory blocks,
103
denotes an address buffer that inputs a row address signal,
104
denotes an address buffer that inputs a column address signal,
105
denotes an address buffer that inputs a block address signal,
106
denotes a row decoder that selects a word line to be accessed in the memory blocks
101
,
102
,
107
denotes a column decoder that selects a bit line pair to be accessed in the memory blocks
101
,
102
, and
108
denotes a block selector that selects the memory blocks
101
,
102
to be accessed.
Further, in
FIG. 11
, reference numeral
109
denotes a sensing amplifier that amplifies potential variations of the bit line pairs that were selected during data read,
110
denotes a writing driver that inputs write data,
111
denotes a data bus,
112
denotes an output buffer that outputs a read data,
113
denotes an input buffer including an input protection circuit, that inputs a write data and converts the data into an internal logic level, and DQ
1
, DQ
2
a data input/output terminal.
FIG. 12
is a circuit diagram to illustrate the internal configuration of the memory blocks
101
,
102
, and in the drawing, a reference numeral
121
denotes a memory cell arrayed in the row and column directions,
122
denotes a bit line load transistor being a load to the bit line,
123
denotes a multiplexer that selects a bit line pair on the basis of the output of the column decoder
107
,
125
denotes a word line to be selected on the basis of the output of the row decoder
106
,
126
denotes a bit line to be selected on the basis of the output of the column decoder
107
through the multiplexer
123
,
127
denotes a pre-charge transistor that beforehand charges the bit line
126
to a level of potential VCC which is the level of a power supply when in a non-selected state,
128
denotes an equalizing transistor connected to two bit lines
126
, that equalizes the levels of the two bit lines
126
when in the non-selected state,
129
denotes an IO line connected to the sensing amplifier
109
and the writing driver
110
shown in FIG.
11
.
FIG. 13
is a circuit diagram to illustrate the internal configuration of the Full CMOS type single port memory cell
121
, and in the drawing, reference
131
denotes denote a driver transistor that holds data,
132
denotes a load transistor that functions as the load to the driver transistor
131
, and
133
denotes an access transistor, being turned ON (to be low resistance) by selecting the word line
125
, connects the bit line
126
and a memory node A or B.
Here, the memory nodes A, B to hold data are connecting points of a drain of the driver transistor
131
, a drain of the load transistor
132
, and a source of the access transistor
133
. But, with regard to a drain and the source of access transistor
133
, it is determined in accordance with a state of the voltage applied. Thus, being composed with a two pairs of inverters composed by the driver transistors
131
and the load transistors
132
, the memory cell holds data by a latch in which an input of one side is mutually connected to an output of the other side.
FIG. 14
is a circuit diagram to illustrate the internal configuration of a high resistance type single port memory cell
121
, and in the drawing, reference numeral
134
denotes a resistor with high resistance that functions as a load to the driver transistor
131
. In
FIG. 14
, the high resistance resistors
134
are used in replacement for the load transistors
132
in the Full CMOS type single port memory cell
121
shown in FIG.
13
. In
FIG. 14
, being composed with the two pairs of inverters composed by the driver transistors
131
and the high resistance resistors
134
, the memory cell holds data by a latch in which an input of one side is mutually connected to an output of the other side.
Next, the operation will be explained.
First, the reading operation will be explained. Complementary data are held at the memory nodes A, B that are connected to the drains of the driver transistors
131
in the memory cell
121
illustrated in
FIG. 13
or FIG.
14
. First, the bit lines
126
are charged in advance to a level of potential VCC which is the level of a power supply the pre-charge transistors
127
.
The row decoder
106
decodes the row address signals, and activates the word line
125
to be accessed to the VCC level. In the memory cell
121
of the selected row, the access transistors
133
are turned ON to flow a column current through the bit lines
126
. This causes the potential of the bit line
126
to become lower on the side of the memory node A or memory node B that holds the L level data. The column decoder
107
decodes the column address signals to input the decoded signal to the multiplexer
123
of the column to be accessed, and selects the bit line pair
126
. The sensing amplifier
109
amplifies the potential variations of the bit line pair
126
that has been selected.
The block selector
108
inputs a block address signal that denotes the memory block
101
or
102
to be accessed, and decodes the input block address signal to generate a block selection signal. The sensing amplifier
109
inputs the block selection signal, and outputs only the data of the selected memory block
101
or
102
to the output buffer
112
through the data bus
111
. The output buffer
112
is a tri-state output buffer, which outputs data to the data input/output terminals DQ
1
, DQ
2
when an external OE signal (output enable signal) is in H level. When the OE signal is in L level, the buffer becomes high impedance, and it does not output data to the data input/output terminals DQ
1
, DQ
2
.
Next, the writing operation will be explained. The input buffer
113
converts the data input from the outside to the input/output terminals DQ
1
, DQ
2
into an internal data level, and outputs the data to the data bus
111
when the external WE signal (write enable signal) is in H level. The block selection signal from the block selector
108
activates the writing driver
110
of the memory block
101
or
102
that has been selected. The activated writing driver
110
outputs the data on the data bus
111
to the IO line
129
of the selected memory block
101
or
102
.
The column decoder
107
activates a pair of multiplexers
123
, which input the data on the IO line
129
into the bit line pair
126
. The row decoder
106
activates one word line
125
to the VCC level to turn ON the access transistors
133
, which writes the data on the bit line pair
126
into one memory cell
121
.
FIG. 15
is a circuit diagram to illustrate internal configuration of a conventional dual port memory cell. The conventional dual port memory cell is made to simultaneously access two memory cells of one and the same memory, and to simultaneously execute the read and writing operations to the one memory. The memory cell provides with two sets of row decoders
106
, column decoders
107
, block selectors
108
, data buses
111
, bit line load transistors
122
, multiplexers
123
, pre-charge transistors
127
, and equalizing transistors
128
for both writing and read. And, as shown in
FIG. 15
, two access transistors
133
,
135
are connected to each of the memory nodes A, B, and two sets of the word lines
125
and the bit lines
126
are wired for writing and read.
Since the semiconductor memory device using the conventional dual port memory cell is compo

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