Semiconductor memory device with decreased current consumption

Details Semiconductor memory device with decreased current consumption Semiconductor memory device with decreased current consumption

1999-12-09

2001-02-06

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S203000, C365S226000, C365S227000, C365S230030, C365S222000

Reexamination Certificate

active

06185137

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to a semiconductor memory device, and more particularly, to a reduction in the power dissipation in a self-refresh operation of a dynamic random access memory (DRAM).
A DRAM used in a portable unit such as a personal computer receives power from a storage battery of the portable unit to perform a self-refresh operation to maintain data which has been written to it. Accordingly, the battery dissipates power to maintain the stored data even when the portable unit is not operating. To preserve power enhance the operable time interval of the portable unit, the power dissipation for the self-refresh operation of the DRAM must be reduced.
FIG. 1
is a schematic block diagram of a conventional DRAM
11
.
The DRAM
11
includes a plurality of cell blocks, four are shown here, BLK
0
-BLK
3
. Each of the cell blocks BLK
0
-BLK
3
comprises a memory cell array
12
, a row decoder
13
, an equalizer
14
, a sense amplifier bank
15
and a column decoder
16
. Only the cell block BLK
0
is shown in detail in FIG.
1
.
The memory cell array
12
comprises a plurality of bit line pairs BL
0
, /BL
0
to BLm, /BLm, a plurality of word lines WL
0
to WLn, and a plurality of memory cells C (see FIG.
2
). Each memory cell C comprises a single transistor and a single capacitor which are connected to an associated intersection of the bit line pairs BL
0
, /BL
0
and the word lines WL
0
to Wln.
The row decoder
13
receives an external address EXAdd provided via a switch
17
as an address signal Add and activates one of the word lines WL. Assume now that a word line WLi is activated by the row decoder
13
as shown in FIG.
2
. The column decoder
16
responds to a column address which is externally supplied to turn on a data bus switch
18
to connect the bit line pair BLi, /BLi to a data bus pair DBi, /DBi. Information stored in the memory cell C is read from the bit line BLi, amplified by the sense amp
15
, and delivered externally on the data bus pair DBi, /DBi.
A refresh operation will now be described. A row control circuit
21
receives a row control signal /RAS and a column control signal /CAS, enters a CBR refresh mode when “CAS before RAS” or CBR condition is detected, which means that the falling edge of the column control signal CAS occurs earlier than that of the row control signal /RAS as shown in
FIG. 3
, and delivers a control signal M
1
to the switch
17
for controlling the CBR refresh operation.
In this mode, the row control circuit
21
delivers a refresh clock signal RCLK to a refresh address counter
22
, which counts the clock signal RCLK to generate a refresh address signal IAdd, which is then applied to the switch
17
. In response to the control signal M
1
, the switch
17
passes the refresh address signal IAdd from the counter
22
to the row decoder
13
of the respective cell block BLK
0
-BLK
3
. The row decoder
13
of the cell block BLK
0
activates the initial word line WL
0
in response to the refresh address signal IAdd. The memory cell C connected to the activated word line WL
0
is then refreshed.
Specifically, referring to
FIG. 2
, the sense amp
15
of the cell block BLK
0
is activated by an H level power supply PSA and an L level power supply NSA, and when activated, amplifies a signal read from the bit line. The memory cell C connected to the activated word line WL
0
is refreshed in this manner.
When the memory cell C is refreshed, a reset operation takes place automatically, thus precharging the bit line.
Specifically, the row control circuit
21
delivers an equalize signal EQ of an H level to the equalizer circuit
14
, which is supplied with a precharge signal PR of a given potential (which may be equal to one-half Vdd, for example) from a bit line precharge circuit
23
, where Vdd is a power supply used to operate various circuits.
As shown in
FIG. 2
, the equalizer circuit
14
comprises a pair of N-channel MOS transistors connected between the bit line pair BLi, /BLi, with the equalize signal EQ being applied to the gates of the transistors and the precharge signal PR being applied to the node between the transistors. In response to the equalize signal EQ of the H level, the equalizer circuit
14
precharges the bit line pair BLi, /BLi to the potential of the precharge signal PR (which is one-half Vdd).
A self-refresh mode is entered after a given time interval has passed from when the memory cell C connected to the initial word line WL
0
of the cell block BLK
0
is refreshed in the CBR refresh mode. In the self-refresh operation, a memory cell C connected to a word line located next to the word line having the refreshed memory cell connected to it (i.e., the second word line WL
1
of the cell block BLK
0
) is similarly refreshed. When a memory cell C connected to the last word line Wln of the cell block BLK
0
has been refreshed, the refresh operation for all the memory cells C in the cell block BLK
0
is completed.
Subsequently, the word lines of the cell block BLK
1
are successively activated to refresh the connected memory cells. In a similar manner, the memory cells C in the cell blocks BLK
2
and BLK
3
are refreshed. When the refresh operation for the memory cell C connected to the last word line of the cell block BLK
3
is completed, the count value of the refresh address counter shown in
FIG. 1
is reset, returning to the initial refresh address or delivering the refresh address signal IAdd for the word line WL
0
of the cell block BLK
0
.
Salvaging of a defect in the memory cell C will now be described. As shown in
FIG. 1
, the DRAM
11
also comprises a redundancy decision circuit
24
, and the memory cell array
12
includes a redundant word line RWL, which is connected to a redundant word line drive circuit
25
in the row decoder
13
.
An address of a defective cell which was previously detected by a test, is stored within the redundancy decision circuit
24
, which determines whether the address Add from the switch
17
coincides with the stored defective address and delivers a redundancy control signal ROM to the row decoder
13
. By way of example, assume that the circuit
24
delivers a redundancy control signal ROM having an H level for the coincidence between the defective address and the address Add. In response to the high redundancy control signal ROM, the row decoder
13
does not activate a word line which was chosen in accordance with the address Add. The redundant word line drive circuit
25
activates the redundant word line RWL in response to the redundancy control signal ROM. As a consequence, a read/write access as well as a refresh operation take place with respect to a memory cell C connected to the redundant word line RWL rather than with respect to the memory cell C connected to the word line at the defective address.
The current consumed during the refresh operation (or refresh current) comprises a DC current component representing a steady-state consumption and an AC current component representing a consumption during the memory cell refresh operation. The DC component represents the consumption by the bit line precharge circuit
23
and the refresh address counter
22
, while the AC component represents the current required for driving the word line WLi and an operating current of the sense amp
15
.
However, it should be noted that if a defective location is replaced by a redundant memory cell which allows a normal read/write operation through an address conversion, this does not physically remove the current consumed by the defective location. That is, there is a current flow through the defective location, which increases the DC component.
As shown in
FIG. 5
, suppose that there is an electrical short circuit across a word line WL and a bit line BL. The sense amp
15
connected to the bit line BL is supplied with the precharge signal PR from the bit line precharge circuit
23
, whereby the bit line BL is precharged to one-half Vdd. On the other hand, the word line WL is connected to a word line drive circuit
26
and is set to a low potential (a g

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