Semiconductor memory device with data scramble circuit

Details Semiconductor memory device with data scramble circuit Semiconductor memory device with data scramble circuit

1997-08-01

1999-07-20

Tu, Trinh L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

714738, 365201, G11C 2900, G01R 3128

Patent

active

059251417

ABSTRACT:
The semiconductor memory device of the present invention comprises a mode setting means for setting the test mode; a circuit for transferring data provided to one of the input/output pins in a group of a given number of input/output pins to each of the rest of the group when the test mode is set; a circuit provided for each input/output pin which, when the test mode is set, selectively inverting the data signal values provided to the input/output pins or retrieved from the memory cells so that the order of the specified logical addresses coincides with the order of the physical addresses of the memory cells; and a circuit for deciding whether or not the data reading operation has been properly performed from the data retrieved from the memory cells to the given number of input/output pins and for sending out a signal indicating the decision to one of the input/output pins in the group of the given number of input/output pins.

REFERENCES:
patent: 5287481 (1994-02-01), Lin
patent: 5844913 (1998-12-01), Hassaum et al.
patent: 5854801 (1998-12-01), Yamada et al.

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