Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1991-02-12
1995-03-14
Callahan, Timothy P.
Static information storage and retrieval
Read/write circuit
Bad bit
36523001, 36523003, 36523006, 36523008, G11C 700, G11C 800
Patent
active
053982061
ABSTRACT:
A semiconductor memory device includes signal lines, a decoder for decoding an inputted address to output the decoded result to some of the signal lines, a matrixed memory array, a part of which being pre-specified as a compensated area, read out means for reading out data from memory cells in an area specified in accordance with a decode signal on the some signal line, a detector for detecting that the address is related with the compensated area from the decode signal on the some signal lines, the compensated area being pre-related with the some signal lines, and a fixed data outputting circuit for merging predetermined data into a predetermined part of the data read out from the memory cells in accordance with the detection signal to output the merged data. The fixed data outputting circuit is controlled by a control circuit in response to a merge control signal to output the data read out from the memory cells without the merging operation.
REFERENCES:
patent: 4663735 (1987-05-01), Novak et al.
patent: 4839860 (1989-06-01), Shinoda et al.
patent: 4901285 (1990-02-01), Sano et al.
patent: 4982372 (1991-01-01), Matsuo
patent: 5005154 (1991-04-01), Masuda
patent: 5034928 (1991-07-01), Isobe
patent: 5043945 (1991-08-01), Bader
patent: 5047983 (1991-09-01), Iwai et al.
patent: 5073873 (1991-12-01), Nogami
patent: 5117382 (1992-05-01), Maejima et al.
patent: 5126973 (1992-06-01), Gallia et al.
patent: 5128896 (1992-07-01), Yamada et al.
patent: 5136535 (1992-08-01), Scharrer et al.
patent: 5146429 (1992-09-01), Kawai et al.
patent: 5155703 (1992-10-01), Nogle
patent: 5179536 (1993-01-01), Kasa et al.
patent: 5193074 (1993-03-01), Anami
patent: 5195057 (1993-03-01), Kasa et al.
Akizawa Mitsuru
Iwasaki Kazuhiko
Noguchi Kouki
Shibata Ryuuji
Yamaguchi Noboru
Callahan Timothy P.
Hitachi , Ltd.
Phan Trong
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