Semiconductor memory device with concurrent refresh and data...

Details Semiconductor memory device with concurrent refresh and data... Semiconductor memory device with concurrent refresh and data...

2001-07-25

2003-03-04

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S207000

Reexamination Certificate

active

06529434

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device that performs a refresh operation.
2. Description of the Related Art
DRAMs (dynamic random access memories) need to periodically refresh data stored in memory cells. Such a refresh operation may be carried out in response to a refresh command supplied from an exterior of the device. Alternately, a pulse signal may be internally generated at refresh intervals, and a refresh operation may be performed at timing indicated by the pulse signal. This eliminates a need to provide a refresh command at every turn from the exterior of the device.
When a refresh operation is performed at refresh timing internally determined inside the semiconductor memory device, data cannot be read or written during refresh cycles. In order to free from and thus make invisible the refresh cycles from the outside, there are certain schemes that make it possible to perform a refresh operation concurrently with a data access operation.
FIG.
1
and
FIG. 2
are timing charts for explaining a scheme that performs a refresh operation concurrently with a data access operation.
FIG. 1
shows a case in which a refresh operation is carried out immediately prior to a data access operation, and
FIG. 2
shows a case in which a refresh operation is carried out immediately following a data access operation. In each figures, (a) shows a word-line activation signal WLR for a word to be refreshed and a word-line activation signal WL
0
for a word to be accessed. A letter designation (b) shows a timing signal brs for performing precharge and equalization processing, and a letter designation (c) shows transfer gate signals ISO
0
and ISO
1
for connecting a sense amplifier to the cell arrays provided on both sides of the sense amplifier. When the transfer gate signal ISO
0
becomes HIGH, the sense amplifier is connected to the cell array on one side. When the transfer gate signal ISO
1
becomes HIGH, the sense amplifier is connected to the cell array on the other side. A letter designation (d) indicates signals psa and nsa for driving a sense amplifier, and a letter designation (e) shows bit-line potentials BL and /BL.
At constant refresh intervals, a refresh signal is generated inside the semiconductor memory device to serve as a pulse signal for triggering a refresh operation. When a data access operation is requested immediately after the generation of a refresh signal, a refresh operation is carried out immediately before the data access operation as shown in
FIG. 1
When a refresh signal is generated during the execution of a data access operation, a refresh operation is performed immediately after the data access operation as shown in FIG.
2
.
In the case of a refresh operation being performed immediately prior to a data access operation, as shown in
FIG. 1
, data of a word to be refreshed is read from a memory cell to a bit line in response to the word-line activation signal WLR, which causes changes in the bit-line potentials BL and /BL. After this, the sense amplifier driving signals psa and nsa are activated to amplify the bit-line potentials BL and /BL. When this amplified data is restored, i.e., is written back to the memory cell of the word to be refreshed, a refresh operation is completed. As shown in
FIG. 1
, (b), the timing signal brs triggers precharge and equalization processing with respect to the bit lines before the start of an actual data access operation. This sets the pair of bit lines to the same precharge potential. Thereafter, a word to be subjected to data access is accessed by the word-line activation signal WL
0
.
In the case of a refresh operation being performed immediately following a data access operation, as shown in
FIG. 2
, data access is followed by a precharge operation first, then followed by the refreshing of memory cells.
If a request for a data access operation is not made within a predetermined time period from the generation of a refresh signal, a refresh operation alone is carried out within a prescribed time period after the refresh signal.
Through the operations as described above, it is possible to obviate a trouble that data access cannot be made during a refresh cycle. Namely, it is possible to make invisible or free from refresh cycles from the outside of the device.
Such operations, however, require both the word-line selection and the data storage operation to be performed twice during a single active cycle. This may result in a problem such as a delay in data access time. An attempt to shorten the cycle may result in an insufficient data restoration time, which may degrade a data-retention capability because of insufficient electric charge in memory cells.
Accordingly, there is a need for a semiconductor memory device that makes a refresh operation invisible from the outside, and shortens a delay in data access time caused by a refresh cycle.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a semiconductor memory device that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor memory device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a semiconductor memory device including bit lines which transfer data of memory cells, a sense amplifier which is connected to the bit lines, and amplifies data on the bit lines that appears in response to an external access, and a latch circuit which is connected to the bit lines, and amplifies and latches data on the bit lines that appears as data to be refreshed.
In the invention as described above, the latch circuit is provided for the purpose of temporarily storing the data to be refreshed. The data to be refreshed is supplied to the latch circuit first. While the latch circuit amplifies and latches the data, a data access operation such as a data read operation or a data write operation is performed. After the completion of the data access operation, the data of the latch is restored in the memory cell to be restored. The present invention makes it possible to concurrently perform the refresh operation with the data access operation, thereby making invisible the refresh cycles from outside the device.
There is no need to perform both a word-line selection and a data-restore operation twice consecutively as in the related art, so that an extension of a data access cycle can be made minimum. This makes it possible to shorten a delay in the data access time compared to the related-art configuration. If a data access is not made concurrently with or within a predetermined time period from the refresh signal, a refresh operation alone is performed.


REFERENCES:
patent: 5701269 (1997-12-01), Fujii
patent: 6154386 (2000-11-01), Ong
patent: 6154405 (2000-11-01), Takemae et al.
patent: 6188624 (2001-02-01), Zheng
patent: 60-197997 (1985-10-01), None
patent: 61-202395 (1986-09-01), None
patent: 3-238692 (1991-10-01), None

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