Semiconductor memory device with column selecting switches...

Details Semiconductor memory device with column selecting switches... Semiconductor memory device with column selecting switches...

2007-02-20

2007-02-20

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S203000, C365S230060, C365S230080

Reexamination Certificate

active

11262801

ABSTRACT:
A semiconductor memory device has column selecting switches in a hierarchical structure. A plurality of local column selecting switches for controlling connections between bit lines and local I/O lines. A global column selecting switch connects column selecting lines and four local column selecting switches when a bit precharging signal becomes low in level for stopping precharging the bit lines. As the column selecting switches are in a hierarchical structure including the global column selecting switch that is directly controlled by the column selecting lines and the local column selecting switches that are controlled by the global column selecting switch, a load on the column selecting lines is reduced for high-speed operation. Even when bit lines are divided into a greater number of bit lines, the number of column selecting switches that are energized by a single column selecting line is not increased, and a signal delay is prevented from occurring.

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