Semiconductor memory device with CMOS-inverter storage cells

Details Semiconductor memory device with CMOS-inverter storage cells Semiconductor memory device with CMOS-inverter storage cells

1994-12-22

1996-07-09

Zarabian, A.

Static information storage and retrieval

Systems using particular element

Ferroelectric

365154, G11C 1140

Patent

active

055351549

ABSTRACT:
A semiconductor memory device in which each storage cell can maintain its content or data value stored therein even if power is lost, and the content or data value thus maintained can be produced when power is on. Each storage cell has first and second CMOS inverters constituting a flip-flop circuit. The first inverter is composed of a first MOS driver transistor and a first thin-film load transistor. The second inverter is composed of a second MOS driver transistor and a second thin-film load transistor. The first and second load transistors have control gate electrodes and ferroelectric PZT films, respectively. The PZT films are dielectrically polarized by voltages applied to the control gate electrodes, so that the threshold voltage difference is generated between the first and second thin-film transistors. Due to the threshold voltage difference, the preceding content or state of the cell is maintained, and then, it can be reproduced when power is supplied again.

REFERENCES:
patent: 5361224 (1994-11-01), Takasu
patent: 5426315 (1995-06-01), Pfiester
H. Ohkubo et al., "16 Mbit SRAM Cell Technologies for 2.0 V Operation", IEDM 1991, pp. 481-484.

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