Static information storage and retrieval – Read/write circuit – Including signal clamping
Patent
1997-02-27
1998-11-10
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Including signal clamping
365204, G11C 1604
Patent
active
058354190
ABSTRACT:
A semiconductor memory device includes: subarrays having memory cells each arranged at cross points of a plurality of bit lines and a plurality of word lines; a row decoder for selecting among the word lines; a column decoder for supplying a select signal to transfer gates for selecting among paired bit lines; and a clamping circuit for fixing the potential of a column select line at a constant potential before the column decoder is activated.
REFERENCES:
patent: 4347586 (1982-08-01), Natsui
patent: 4513399 (1985-04-01), Tobita
patent: 4610002 (1986-09-01), Kaneko
patent: 4760559 (1988-07-01), Hidaka et al.
patent: 5161121 (1992-11-01), Cho
patent: 5204842 (1993-04-01), Umeki
patent: 5307307 (1994-04-01), Wada et al.
patent: 5363331 (1994-11-01), Matsui et al.
patent: 5465233 (1995-11-01), Slemmer
Hayashikoshi Masanori
Ichimura Tooru
Okimoto Hiromi
Tobita Youichi
Ho Hoai
Mitsubishi Denki & Kabushiki Kaisha
Nelms David C.
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