Semiconductor memory device with circuit for isolating arrayed m

Details Semiconductor memory device with circuit for isolating arrayed m Semiconductor memory device with circuit for isolating arrayed m

1992-02-27

1993-09-14

LaRoche, Eugene R.

Static information storage and retrieval

Systems using particular element

Semiconductive

365185, 365104, 365206, 36518904, G11C 702, G11C 1602

Patent

active

052455696

ABSTRACT:
A semiconductor memory device has an array of memory cells which are accessed by digit and word lines. The device includes a digit line controller for selecting a digit line to access a preselected memory cell and for applying an activation voltage to the selected digit line. The device also has an isolation voltage generator for generating an isolation voltage. An isolating circuit then transfers the isolation voltage to digit lines immediately adjacent to the selected digit line to isolate neighboring memory cells from the memory cell being accessed. This isolation voltage effectively reduces or eliminates parasitic leakage between neighboring memory cells in high voltage and highly integrated memories.

REFERENCES:
patent: 4458348 (1984-07-01), Fukuda et al.
patent: 4888734 (1989-12-01), Lee et al.
patent: 5027321 (1991-06-01), Park

Affiliated with

Also associated with

Rating

Semiconductor memory device with circuit for isolating arrayed m does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device with circuit for isolating arrayed m, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device with circuit for isolating arrayed m will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2033178