Semiconductor memory device with bus driver circuit...

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture

Reexamination Certificate

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Details

C710S316000, C365S185210, C365S189050

Reexamination Certificate

active

11090357

ABSTRACT:
A semiconductor memory device includes first to third data buses, and first and second connection circuits. The first connection circuit inverts and transfers a first output signal on the first data bus read out from a memory onto the second data bus in response to a first selection signal, inverts and transfers a second output signal on the second data bus read out from the memory onto the first data bus in response to a second selection signal, and connects the first and second data buses in response to a reset signal. The second connection circuit inverts and transfers the inverted first output signal on the second data bus onto the third data bus in response to the first selection signal and transfers the second output signal on the second data bus onto the third data bus in response to the second selection signal.

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patent: 5936888 (1999-08-01), Sugawara
patent: 5973963 (1999-10-01), Sugawara
patent: 6064592 (2000-05-01), Nakagawa et al.
patent: 6064597 (2000-05-01), Takeshima et al.
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patent: 6687166 (2004-02-01), Takahashi et al.
patent: 6788600 (2004-09-01), Sugawara et al.
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patent: 2005/0223152 (2005-10-01), Sugawara
patent: 2000-149565 (2000-05-01), None
“A 1.8-V 128Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor” by Sim et al. (abstract only) Publication Date: Apr. 2003.

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