Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2000-03-08
2001-11-27
Helms, David (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S233100, C365S236000, C365S189050
Reexamination Certificate
active
06324115
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor memory devices and, more particularly, to a semiconductor memory device having a burst mode access.
BACKGROUND OF THE INVENTION
In order to improve the access speed of a memory device, a burst mode access function can be provided for the memory device. A burst mode access read of the memory device can start at any memory location and can continue for any number of memory locations. In such a memory, any number of memory locations, not only groups of four memory locations, can be read consecutively in burst mode. Sequential memory access is consequently quite fast.
In an example, the burst mode access is provided as follows. The memory array is divided into two memory banks. Each memory bank includes half of the columns of the memory array. Each memory bank has its own row and column decoders that can access the corresponding memory bank independent of the other side. The columns of each memory bank are divided into predetermined groups of columns. A sense amplifier circuit is provided for each group in each memory banks.
In accordance with burst mode access, data in the memory banks is sensed through the corresponding sense amplifier circuits simultaneously. Data thus sensed from both memory banks is held in data registers. First, data from the data register corresponding to one memory bank is transferred to the exterior. Then, data from the data register corresponding to the other memory bank is transferred to the exterior, and, at the same time, data is sensed from the next location in the first memory bank, through its attached sense amplifier circuit.
An example of a memory device with an above-mentioned burst mode access is disclosed in U.S. Pat. No. 5,559,990, entitled MEMORIES WITH BURST MODE ACCESS, which is incorporated by reference herein.
It is well known in the art that power noise (often referred to as “input/output (IO) noise”) accompanies data output signaling. If data in one memory bank is sensed at the same time that data corresponding to another memory bank is being output, the data sensing operation may be affected by power noise. As a result, it is impossible to ensure a stable data sensing operation for a memory device during burst mode access.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a burst mode semiconductor memory device having immunity against power noise-induced sensing errors.
It is another object of the invention to provide a burst mode semiconductor memory device capable of ensuring stable data sensing operations.
In order to attain the above objects, according to one aspect of the present invention, a semiconductor memory device with a burst access mode is provided. The memory device comprises a memory array, a counter circuit, a data sensing-control circuit, and a data-reading circuit. The memory array comprises first and second memory banks, each comprising a plurality of memory cells for storing multi-level data. The first and second memory banks are read independently from each other. The counter circuit receives externally applied address bit signals to count up the address bit signals in synchronization with a read enable clock signal. And, the data-sensing control circuit receives one of the address bit signals counted up by the counter circuit and generates a set of data-sensing control signals when the one address bit signal transitions. The one address bit signal is used for bank selection. The data-reading circuit operates responsive to the data-sensing control signals, and senses multi-level data from the first and second memory banks alternately.
According to the device, the data reading circuit holds the multi-level data sensed from one of the memory banks and, at the same time, senses multi-level data from the other of the memory banks during a data sensing operation. And, during the data sensing operation for the other memory bank, the multi-level data held in the data reading circuit is output sequentially to the exterior in synchronization with the read enable clock signal and in accordance with the combination of the others of the address bit signals thus counted up.
According to the device, the data sensing control circuit comprises an address transition detecting section for generating a first address transition detection signal in a pulse form when the one address bit signal transitions from a first logic level to a second logic level, and for generating a second address transition detection signal in a pulse form when the one address bit signal transitions from the second logic level to the first logic level; a sensing start signal generating section for generating a sensing start signal in a pulse form in response to the first address transition detection signal, the second address transition detection signal or a chip activation signal; a clock generating section for generating a plurality of clock signals in response to a clock control signal, wherein the clock signals of the plurality each have a different period; a sensing control signal generator for generating the sensing control signals in response to the clock signals during the data sensing operation; a sensing period detector for activating a sensing period detection signal indicating the period of the data sensing operation in response to the sensing start signal, wherein the sensing period detector receives the clock signals, detects whether the data sensing operation is ended, and inactivates the sensing period detection signal in accordance with the detection result; and a clock controller responsive to the sensing start signal, for activating the clock control signal during the activation of the sensing period detection signal so as to generate the clock signals, wherein the clock controller inactivates the clock generating section at the inactivation of the sensing period detection signal.
According to the semiconductor memory device of the present invention, a bit line precharge operation of each sensing period starts in synchronization with the read enable clock signal. Since no sensing of each sensing period is performed at a transition timing of the read enable clock signal, this burst access mode semiconductor memory device has immunity against power noise, resulting in a stable data sensing operation.
REFERENCES:
patent: 5457650 (1995-10-01), Sugiura et al.
patent: 5559990 (1996-09-01), Cheng et al.
patent: 5768188 (1998-06-01), Park et al.
patent: 6031785 (2000-02-01), Park et al.
patent: 6134178 (2000-10-01), Yamazaki et al.
Helms David
Lam David
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
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