Semiconductor memory device with built-in self-diagnostic...

Details Semiconductor memory device with built-in self-diagnostic... Semiconductor memory device with built-in self-diagnostic...

2003-02-24

2004-11-16

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S189011

Reexamination Certificate

active

06819609

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor memory device with a built-in self-diagnostic function and a semiconductor device having this semiconductor memory device. Particularly, this invention relates to a semiconductor memory device having a self-diagnostic test function which enables flexible adjustment to a change of test specification.
2. Description of the Related Art
To test a recent large-capacity high-speed semiconductor memory device, a tester needs to operate at a high speed. Particularly a tester necessary for testing a high-speed synchronous semiconductor memory device is required to operate at a very high speed and the tester itself is expensive. Moreover, depending on increase in operation frequency of the semiconductor memory device, the tester cannot follow the increased operation frequency.
As systems have become more and more advanced and complicated, a built-in semiconductor memory device with a large capacity is provided as a memory module in a high-performance semiconductor device called system LSI. In some cases, for such a semiconductor memory device as a built-in module, a terminal group for inputting/outputting addresses, data, commands and the like is not provided as a terminal group of the semiconductor device and testing of the semiconductor memory device cannot be carried out from the outside.
Thus, if a built-in self-test (hereinafter referred to as BIST) circuit for carrying out self-diagnosis of the memory is provided in the semiconductor memory device or in the semiconductor device having the semiconductor memory device as a memory module, testing can be carried out without using an expensive tester for the large-capacity high-speed semiconductor memory device and irrespective of the presence/absence of a test terminal for the memory module built-in the semiconductor device.
As an example of the semiconductor memory device having such a BIST circuit, a semiconductor memory device is described in the JP Laid-Open Patent Publication No.2001-148199, in which a program for carrying out self-test loaded in advance in a command RAM
50
is sequentially read out in accordance with a program counter value outputted from an ALPG
54
, thus testing a memory-cell array
30
, and the test result is outputted via an input/output and BIST write/judgment circuit
32
, as shown in FIG.
18
. The loading of the program to the command RAM
50
is carried out as a BIST controller
62
functions as a load sequencer for the program. It is a semiconductor memory device in which testing is carried out while changing data and command patterns by loading the program for test to the command RAM
50
from the outside.
However, in the case where testing by a BIST circuit built in a semiconductor memory device or a memory module of a semiconductor device constituted on the basis of memory specifications established at the time of design, if the number of types of write data patterns to each memory cell by BIST increases, the circuit scale of the BIST circuit expands and the proportion of the BIST circuit region to a memory main circuit region which functions as a semiconductor memory device, on a chip die, increases, as shown in FIG.
16
. Therefore, increase in overhead due to the occupied area of the BIST circuit on the chip causes a problem of increase in chip size and chip cost.
In the case where a built-in semiconductor memory device is provided as a memory module in a semiconductor device, generally, the required memory capacity differs depending on the specifications of a system in which the semiconductor device is used. Thus, in expanding types of semiconductor device, in order to reduce the time and cost for development and manufacture, a memory module is designed in accordance with a maximum memory capacity required for the type expansion and only module structures such as memory capacity, address length, bus width, burst length that are necessary for individual types are used.
In this case, however, the test specifications of the BIST circuit need be adjusted to each of the actually used memory modules. Memory modules having a maximum permissible memory capacity must be provided and the BIST circuit must be redesigned for each type despite the reduction in time and cost for redevelopment and remanufacture of the memory modules, which is a problem. For example, as shown in
FIG. 17
, if two megabits are used for an eight-megabit memory module as a memory main circuit, a BIST circuit for two megabits (
FIG. 17
, (A)) is necessary. A BIST circuit for four megabits (
FIG. 17
, (B)) is necessary in the case of four megabits, and a BIST circuit for eight megabits (
FIG. 17
, (C)) is necessary in the case of eight megabits. Moreover, with respect to the bus width, a BIST circuit for ×8 bits (
FIG. 17
, (D)) is necessary in the case of ×8 bits. A BIST circuit for ×16 bits (
FIG. 17
, (E)) is necessary in the case of ×16 bits, and a BIST circuit for ×32 bits (
FIG. 17
, (F)) is necessary in the case of ×32 bits.
Once the BIST circuit is installed, its operation specifications cannot be changed, causing a problem that change and addition of write data patterns and change of the test specifications cannot be carried out.
The change of the test specifications in the BIST circuit is possible by using a semiconductor memory device described in the JP Laid-Open Patent Publication No.2001-148199. However, in the semiconductor memory device of the JP Laid-Open Patent Publication No.2001-148199, the command RAM
50
made of an SRAM, the ALPG
54
and the like must be provided for storage of programs, operation control and the like. Therefore, the BIST circuit needs complicated control. There arise problems such as a longer development period due to the complicated circuit structure and increase in overhead on the chip die due to the need for a large occupied area on the chip.
SUMMARY OF THE INVENTION
In order to solve at least one of the problems of the above-described conventional techniques, it is an object of the present invention to provide a semiconductor memory device having a self-diagnostic test function which enables flexible adjustment to change and addition of test specifications without having a complicated and large-scale circuit structure to perform complicated control in self-diagnostic test, or to provide a semiconductor device having the semiconductor memory device as a memory macro.
In order to achieve the above-described object, a semiconductor memory device or a semiconductor device having a semiconductor memory device as a memory macro according to one aspect of the present invention includes a semiconductor memory device having a self-diagnostic test function, the semiconductor memory device comprising a memory operation specification information storing unit in which memory operation specification information that is rewritable from the outside is stored, wherein an operation parameter in self-diagnostic test is set on the basis of the memory operation specification information.
A semiconductor memory device or a semiconductor device having a semiconductor memory device as a memory macro according to another aspect of the present invention includes a semiconductor memory device having a self-diagnostic test function, the semiconductor memory device comprising a test specification information storing unit in which test specification information that is rewritable from the outside is stored, wherein operation specification in self-diagnostic test is set on the basis of the test specification information.
In the semiconductor memory device or the semiconductor device having a semiconductor memory device as a memory macro according to one aspect or another aspect of the present invention, a memory operation specification information storing unit in which memory operation information that is rewritable from the outside is stored, or a test specification information storing unit in which test specification information that is rewritable from the outside is stored, is provi

Affiliated with

Also associated with

Rating

Semiconductor memory device with built-in self-diagnostic... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device with built-in self-diagnostic..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device with built-in self-diagnostic... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3331449