Semiconductor memory device with bit line potential compensation

Details Semiconductor memory device with bit line potential compensation Semiconductor memory device with bit line potential compensation

1995-12-26

1997-07-08

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365203, 257903, G11C 700

Patent

active

056468954

ABSTRACT:
The semiconductor memory device as static RAM disclosed comprises a memory cell array, a plurality of load circuits, and a plurality of bit line potential compensation circuits. Each of the bit line potential compensation circuits is a pseudo memory cell and is provided between each of the bit line load circuits and the memory cell array for holding the power supply potential supplied. The pseudo memory cell has an element arrangement equivalent to that of each of the memory cells. The pseudo memory cell has a pair of thin film transistors each having a source electrode commonly held at the power supply potential and a drain electrode connected to the gate electrode of the other, the drain electrode of one of the thin film transistors being connected through a third transfer transistor to the first bit line, the drain of the other thin film transistor being connected through a fourth transfer transistor to the second bit line, the gate electrodes of the third and fourth transfer transistors being held at the power supply potential. With this arrangement, it is possible to make a substantial reduction in the element area of the structure.

REFERENCES:
patent: 5508961 (1996-04-01), Han

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