Semiconductor memory device with bit line of small...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C438S257000

Reexamination Certificate

active

10896060

ABSTRACT:
A reduction of a resistance of a bit line of a memory cell array and a reduction of a forming area of the memory cell array are planed.Respective bit lines running at right angles to a word line are composed of a diffusion bit line formed in a semiconductor substrate and a linear metal bit line on an upper side of the diffusion bit line. The diffusion bit line is formed in a linear pattern on a lower side of the metal bit line in the same manner, and the metal bit line is connected with the diffusion bit line between the word lines. An interlayer insulating film is formed on the memory cell array, and the metal bit line is formed with being buried in it.

REFERENCES:
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patent: 5717635 (1998-02-01), Akatsu
patent: 6174758 (2001-01-01), Nachumovsky
patent: 6218695 (2001-04-01), Nachumovsky
patent: 6512263 (2003-01-01), Yuan et al.
patent: 1998-053139 (1998-09-01), None
Eitan, Boaz., et al. “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?”, Presented at the International Conference on Solid State devices and Materials. 1999, Tokyo, pp. 3.
Office Action dated May 26, 2006.

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