Semiconductor memory device with bit line contact areas and stor

Details Semiconductor memory device with bit line contact areas and stor Semiconductor memory device with bit line contact areas and stor

1996-06-25

1998-09-22

Zarabiu, A.

Static information storage and retrieval

Systems using particular element

Capacitors

365 63, G11C 1124

Patent

active

058124446

ABSTRACT:
A semiconductor memory device includes a plurality of memory cells located at intersections of the word lines and the bit lines, each of the memory cells having a capacitor for storing information and a transfer transistor for reading information from and writing information into the capacitor, the gate of the transfer transistor being connected to a word line, the source of the transfer transistor being connected through a bit line contact area to a bit line, the drain of said transfer transistor being connected through a storage capacitor contact area to the storage electrode of the capacitor. A memory cell pair is formed by two nearby memory cells and these two memory cells of the memory cell pair have a common bit line contact area. In a unit region defined by word line Nos. "i" and "i+1" and bit line Nos. "j" and "j+4", there are provided bit line contact areas and storage capacitor contact areas with a ratio of 1:2 between the number of the bit line contact areas and the storage capacitor contact areas.

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