Semiconductor memory device with an improved erroneous write cha

Details Semiconductor memory device with an improved erroneous write cha Semiconductor memory device with an improved erroneous write cha

1992-07-07

1993-10-12

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257320, 257324, H01L 29788, H01L 29792

Patent

active

052528464

ABSTRACT:
A semiconductor memory device containing a number of memory cells each having a floating gate, an erase gate, and a control gate. In a data erasure mode, electrons are discharged from the floating gate into the erase gate. In the semiconductor memory device, an impurity concentration in at least a region of the floating gate overlapping with the erase gate is lower than that of the erase gate.

REFERENCES:
patent: 3996657 (1976-12-01), Simko et al.
patent: 4119995 (1978-10-01), Simko
patent: 4437172 (1984-03-01), Masuoka
patent: 4437174 (1984-03-01), Masuoka
patent: 4466081 (1984-08-01), Masuoka
patent: 4812898 (1989-03-01), Sumihiro
patent: 4996572 (1991-02-01), Tanaka et al.
IEEE Cat. No. 84 CH 2061-0, Sep. 10-12, 1984/San Diego, "Poly-oxide
itride/oxide structures for highly reliable EPROM cells" by S. Mori et al.
Masuoka et al., A Flash E.sup.2 PROM Cell Using Triple Polysilicon Technology, Proceedings of the IEEE International Electron Devices Meeting, Dec. 9-12, 1984.

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