Semiconductor memory device with address transition actuated dum

Static information storage and retrieval – Read/write circuit

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Details

365210, 36518907, 3652335, G11C 700, G11C 11413, G11C 1606

Patent

active

051915529

ABSTRACT:
In a semiconductor memory device, a first load circuit is coupled with the column lines, first dummy cells are connected to a dummy column line, a second load circuit is connected to the dummy column line, a second dummy cell is connected to the dummy column line, and a sense amplifier senses the data stored in the memory cell in accordance with a potential difference between the column line and the dummy column line. In semiconductor memory devices thus arranged, the second dummy cell is set in an on state normally. The connection of the second dummy cell with the dummy line changes a current flowing to the dummy line at the time of row line switching, thereby to hold back a rise of the reference potential at the time of the row line switching.

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