Semiconductor memory device with active pull up

Details Semiconductor memory device with active pull up Semiconductor memory device with active pull up

1991-02-28

1993-11-30

Dixon, Joseph L.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365193, 365203, 365204, G11C 700, G11C 1140

Patent

active

RE0344630

ABSTRACT:
A MOS dynamic type RAM comprises memory cells (10), dummy cells (11), bit line pairs (BL, BL), word lines (WL), dummy word lines (DWL) and sense amplifiers (12). In a non-active cycle, the potentials of each pair of bit lines (BL, BL) are precharged at 1/2 of a supply potential V.sub.CC. Each sense amplifier (12) operates in an active cycle following the non-active cycle, while each active pull-up circuit (13) pulls up the potential of a higher level one of the pair of bit lines to V.sub.CC. This active cycle is defined by an internal RAS internal signal, which is generated by a NAND circuit (27) in response to an external RAS signal and an RPW signal obtained by delaying the external RAS signal by a delay circuit (20) and having a trailing edge obtained by delaying the trailing edge of the external RAS signal by a prescribed period.

REFERENCES:
patent: 4291392 (1981-09-01), Proebstring
patent: 4528646 (1985-07-01), Ochii et al.
patent: 4543501 (1985-09-01), McAlexander, III et al.
patent: 4601017 (1986-07-01), Mochizuki et al.
patent: 4633443 (1986-12-01), Childers
patent: 4638459 (1987-01-01), Pechar, Jr. et al.
patent: 4677313 (1987-06-01), Mimoto

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