Semiconductor memory device with a test mode

Details Semiconductor memory device with a test mode Semiconductor memory device with a test mode

1999-11-17

2003-12-02

Chung, Phung M. (Department: 2784)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000

Reexamination Certificate

active

06658609

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a test mode.
In recent years, the increase in the capacity of semiconductor memory devices has increased the time required for testing such devices. One of the tests is the application of stress to the memory cell array. It is desirable that the stress application test be conducted within a short period of time.
To guarantee the reliability of a semiconductor memory device, an acceleration test is conducted on the device before it is shipped out of the factory. The acceleration test is conducted under high temperature and high pressure conditions by applying stress to the internal circuits of the chip. The level of the stress exceeds the level of the stress applied during normal usage. Initial stage failures are screened out through the acceleration test. Such test is normally referred to as burn-in. The burn-in is conducted on word lines by applying stress to the word lines. That is, voltage, the level of which is increased and decreased, is selectively applied to the word lines. In a normal mode, the word lines are selected in sequential order. In a test mode, all of the word lines are selected simultaneously.
However, when the word lines are selected in sequential order, the test time increases proportionally to the number of word lines. When all of the word lines are selected simultaneously, although DC stress, in which the potential difference between predetermined word lines is null, can be applied, AC stress, in which a potential difference occurs between word lines, cannot be applied.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor memory device that is capable of applying DC/AC stress to word lines within a short period of time.
To achieve the above object, the present invention provides a semiconductor memory device including a memory cell array having a plurality of memory cells, each arranged at an intersection between one of a plurality of word lines and one of a plurality of bit lines. The plurality of word lines form a plurality of word line groups. The semiconductor memory device also includes a plurality of driver circuits, each connected to one of the plurality of word line groups. A first decoder circuit is connected to the plurality of driver circuits to selectively activate the driver circuits. A second decoder circuit is connected to the plurality of driver circuits to select predetermined ones of the word lines in each of the plurality of word line groups. The first decoder circuit substantially simultaneously activates the plurality of driver circuits in response to a test mode signal and the second decoder circuit selects the predetermined word lines in predetermined patterns in response to the test mode signal.
In a further aspect of the present invention, a semiconductor memory device includes a memory cell array having a plurality of memory cells, each arranged at an intersection between one of a plurality of word lines and one of a plurality of bit lines. The plurality of word lines form a plurality of first word line groups and a plurality of second word line groups., A plurality of first driver circuits and a plurality of second driver circuits are connected to the plurality of first word line groups and the plurality of second word line groups, respectively. A first decoder circuit is connected to the plurality of first driver circuits and the plurality of second driver circuits to selectively activate the first and second driver circuits. A second decoder circuit is connected to the plurality of first driver circuits and the plurality of second driver circuits to select predetermined word lines in each of the plurality of first and second word line groups. The first decoder circuit substantially simultaneously activates the plurality of first and second driver circuits in accordance with a test mode signal and the second decoder circuit selects the predetermined word lines in predetermined patterns in accordance with the test mode signal.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.


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