Semiconductor memory device with a stacked-bank architecture...

Details Semiconductor memory device with a stacked-bank architecture... Semiconductor memory device with a stacked-bank architecture...

2008-01-15

2008-01-15

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060

Reexamination Certificate

active

07319631

ABSTRACT:
A semiconductor memory device having a stacked-bank architecture capable of activating the word lines coupled to memory cells selectively with respect to the memory banks is disclosed. The semiconductor memory device includes memory bank groups and a decoder unit. Each of the memory bank groups includes a plurality of memory banks arranged in a stacked-bank architecture. The decoder unit generates a decoded row address signal to individually select one of the memory banks in response to an external address signal under the control of an output enable signal. Accordingly, the semiconductor memory device having a stacked-bank architecture capable of activating the word lines coupled to memory cells selectively with respect to the memory banks has lower power consumption and operates stably against noise.

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patent: 6603683 (2003-08-01), Hsu et al.
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patent: 2003-007062 (2003-01-01), None
patent: 2000-0018314 (2000-04-01), None

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