Semiconductor memory device with a self refresh mode

Details Semiconductor memory device with a self refresh mode Semiconductor memory device with a self refresh mode

2002-01-18

2003-11-25

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S233100

Reexamination Certificate

active

06654302

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to a semiconductor memory device and more specifically to a semiconductor memory device, such as a DRAM (dynamic random access memory) having a self refresh mode and an externally applied exit command.
BACKGROUND OF THE INVENTION
A dynamic random access memory (DRAM) includes memory cells for storing data. In order to prevent data loss, the memory cells must be refreshed within a specified time period. One mode of operation of a DRAM is a self refresh mode. When a self refresh mode command is executed, data stored in the memory cells is automatically refreshed while the DRAM is in a standby state. In the standby state, the system (such as a computer system in which the DRAM is included) may be excluded from accessing the DRAM. During the operation of the self refresh mode, the system is not reading from or writing data to the DRAM, thus, it is desirable to reduce power consumption by disabling unused circuitry on the DRAM.
Referring now to
FIG. 3
, a circuit schematic diagram of a portion of a conventional semiconductor memory device is set forth. The portion of a conventional semiconductor device of
FIG. 3
is disclosed in Japanese Laid-Open Patent Publication No. Hei-7-65574 (JP 07065574 A). The conventional semiconductor device is a synchronous DRAM.
The portion of a conventional semiconductor memory device includes initial stage circuits (
1
to
3
), refresh command decision circuit
4
, self refresh mode decision circuit
5
and an inverter
6
.
Initial stage decision circuit
1
receives a self refresh latch signal SRS, a reference voltage Vref and an external clock ECK and provides an internal clock ICLK. Initial stage decision circuit
2
receives self refresh latch signal SRS, reference voltage Vref and a clock enable signal CKE and provides signal S
1
. Initial stage decision circuit
3
receives self refresh latch signal SRS, clock enable signal CKE and provides signal S
2
. Refresh command decision circuit
4
receives internal clock ICLK and external signals (/RAS, /CAS, /WE, and /CS) and provides a refresh command signal RC. Self refresh mode decision circuit
5
receives internal clock ICK, signal S
1
, and signal S
2
and provides a signal S
3
. Inverter
6
receives signal S
3
and provides self refresh latch signal SRS.
Initial stage circuit
1
includes a current mirror type receiver and is enabled when self refresh status latch signal SRS is at a low logic level. The initial stage circuit
1
outputs internal clock ICK. Internal clock ICK is a clock used in the conventional semiconductor memory device and is derived from external clock ECK. External clock ECK is a reference clock provided on the system.
Initial stage circuit
2
includes a current mirror type receiver and is enabled when self refresh status latch signal SRS is at the low logic level. Initial stage circuit
2
detects the logic level of clock enable signal CKE. The logic level of clock enable signal CKE determines whether or not external clock signal ECK is valid. When clock enable signal CKE is high and refresh status latch is low, initial stage circuit
2
provides signal S
1
having a high level. However, when clock enable signal CKE is low, initial stage circuit
2
provides signal S
1
having a low level.
Initial stage circuit
3
includes a complementary logic gate and is enabled when self refresh status latch is at the high logic level. Initial stage circuit
3
detects the release (exit) of the self refresh mode. The self refresh mode is exited when clock enable signal CKE transitions from the low logic level to the high logic level. In this case, initial stage circuit
3
provides signal S
2
having a low level.
Refresh command decision circuit
4
detects an externally applied refresh command. The refresh command is provided by a low level row address strobe signal /RAS, a low level column address strobe signal /CAS, a low level chip select signal /CE, and a high level write enable signal /WE in synchronism with the rising edge of internal clock ICLK. Prefix “/” indicates negative logic. When a refresh command is detected, refresh command decision circuit
4
provides a refresh command signal RC having a high logic level.
Self refresh mode decision circuit
5
includes D-type flip-flop
7
, D-type latch
8
, NAND gate
9
, and inverters (
10
,
11
, and
12
). When the refresh command signal RC indicates a refresh entry (set) to the self refresh mode, self refresh mode decision circuit
5
outputs signal S
3
having a low logic level. Inverter
6
receives the low signal S
3
and outputs self refresh latch signal SRS having a high logic level.
Referring now to
FIG. 4
, a timing diagram illustrating a conventional self refresh operation is set forth. The operation of the portion of the semiconductor memory device will now be described with reference to
FIG. 4
in conjunction with FIG.
3
.
Clock enable signal CKE is initially high before time t
1
and transitions low at time t
3
. Also, because a refresh entry to the self refresh mode has not been executed, refresh command signal RC is low before time t
3
. Because refresh command signal RC is low, NAND gate
9
provides a high output as signal S
3
from self refresh mode decision circuit
5
. With signal S
3
at the high level, inverter
6
provides a low output as self refresh latch signal SRS.
With self refresh latch signal SRS low, initial stage circuits (
1
and
2
) are in an enabled state and initial stage circuit
3
is in a disabled state. In this way, initial stage circuit
1
outputs internal clock ICK by delaying external clock ECK by a predetermined time as illustrated in FIG.
4
. Initial stage circuit
2
receives the high clock enable signal CKE and outputs a high level signal S
1
. When in the disabled state, initial stage circuit
3
outputs a high level signal S
2
.
A refresh entry command is executed at time t
3
. This is done by providing clock enable signal CKE, row address strobe signal /RAS, column address strobe signal /CAS, and chip select signal /CS at a low level and write enable signal /WE at a high level at the rising edge of external clock ECK at time t
3
. Refresh command decision circuit
4
receives the refresh entry command and generates a refresh command signal RC having a high level in synchronism with internal clock ICK.
When clock enable signal CKE goes low, initial stage circuit
2
outputs signal S
1
having a low level. After subsequent high and low transitions of internal clock ICLK, signal S
1
propagates through D-type flip-flop
7
and D-type latch
8
to provide a signal S
4
having a high level at time t
4
. With refresh command signal RC high and signal S
4
high, NAND gate
9
provides a low signal S
3
and inverter
6
provides self refresh status latch signal SRS having a high level after time t
4
.
With self refresh status latch signal SRS high, initial stage circuits (
1
and
2
) are disabled and initial stage circuit
3
is enabled. In this way, initial stage circuit
1
outputs internal clock ICK fixed at a high level regardless of the logic level of external clock ECK. Likewise, initial state circuit
2
outputs signal S
1
having a low level. Because at this time clock enable signal CKE is kept low, initial stage circuit
3
provides signal S
2
having a high level. By keeping ICLK high, self refresh mode decision circuit
5
keeps data latched in internal D-type flip-flop
7
and D-type latch
8
is not modified and the self refresh mode remains set. Thus, signal S
4
is kept at the high level. Also, by keeping internal clock ICLK high, refresh command decision circuit
4
does not identify further applied commands and refresh command signal RC remains high as illustrated in FIG.
4
.
Then, at around time t
7
, clock enable signal CKE transitions high. With clock enable signal CKE high, initial stage circuit
3
outputs signal S
2
at a low level irrespective of the rising edge of external clock ECK. When signal S
2
goes low, D-type latch
8
is reset to provide a high output and to cause signal S
4
to go low.

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