Semiconductor memory device with a self-initializing circuit ope

Details Semiconductor memory device with a self-initializing circuit ope Semiconductor memory device with a self-initializing circuit ope

1995-04-28

1995-12-19

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Signals

365193, 365233, 365222, G11C 1134

Patent

active

054774918

ABSTRACT:
An improved DRAM includes an internal circuit to be initialized upon start of supply of a supply voltage. The DRAM includes a dummy clock signal generator, and applies a dummy clock signal to a clock signal generator through a switching circuit until a predetermined time period elapses after the start of supply of the supply voltage by a timer circuit. A signal /RAS is controlled in a special manner, is not required for initializing an internal circuit such as a refresh counter. Therefore, a load required in the external circuit for initialing the DRAM is reduced.

REFERENCES:
patent: 4716551 (1987-12-01), Inagaki
patent: 4933902 (1990-06-01), Yamada et al.
patent: 5278792 (1994-01-01), Inoue et al.
"80386 Hardward Reference Manual", Intel Literature Sales, Santa Clara, Calif., 1987, pp. 6-15-6-28.

Affiliated with

Also associated with

Rating

Semiconductor memory device with a self-initializing circuit ope does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device with a self-initializing circuit ope, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device with a self-initializing circuit ope will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-996971