Semiconductor memory device with a potential level-setting circu

Details Semiconductor memory device with a potential level-setting circu Semiconductor memory device with a potential level-setting circu

1990-02-07

1991-01-01

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365154, 365202, G11C 700

Patent

active

049823655

ABSTRACT:
During a data-clearing operation, while maintaining in the OFF state the transfer gate transistors in each of the static type memory cells associated with at least one column, the source of one of two drive transistors incorporated in the memory cell is set to a high potential level, and the source of the other drive transistor to a low level. As a result, the clearing operation is performed to a minimum of 1 column in the memory cell matrix. Due to the arrangement of the memory device, no address-selecting operation is required for selecting a memory cell during the clearing operation. Moreover, the clearing operation is carried out in a minimum unit of 1 column in the memory cell matrix. Consequently, the processing time for the clearing operation is reduced. Furthermore, the DC current flowing during the clearing operation is reduced, since the transfer gate transistor in the memory cell is maintained in the OFF state during the clearing operation, with the result that the power consumption is lowered.

REFERENCES:
patent: 4780847 (1988-10-01), Ito
patent: 4874686 (1989-11-01), Suzuki et al.

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