Semiconductor memory device with a laser programmable redundancy

Details Semiconductor memory device with a laser programmable redundancy Semiconductor memory device with a laser programmable redundancy

1984-10-30

1987-04-14

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Bad bit

365203, G11C 700

Patent

active

046583793

ABSTRACT:
A semiconductor memory device with a laser programmable redundancy circuit, which includes: a plurality of decoders for selecting a row or column of the memory; at least one spare decoder which is selected instead of a decoder connected to a faulty memory cell; a link element inserted in series with the precharging transistor and connected between the power supply and the decoder output line; a signal generator which generates a non-selection signal for making the object decoder unselected only when a spare decoder is selected, the signal generator being provided in the spare decoder; and a transistor, having a gate to which the non-selection signal is input, with the drain and the source thereof being connected to the decoder output and ground, respectively, the transistor being provided in the decoder.

REFERENCES:
patent: 4538247 (1985-08-01), Venkateswaran
"Laser Programmable Redundancy and Yield Improvement in 64K DRAM", Smith et al, IEEE Journal, Oct. 1981.
"A Low-Power Sub 100 ns 256K Bit Dynamic RAM", Fujii et al, IEEE Journal, Oct. 1983.
"A 256K Dynamic RAM with Page-Nibble Modes", Fujishima et al, IEEE Journal, Oct. 1983.

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