Semiconductor memory device with a decoupling capacitor

Details Semiconductor memory device with a decoupling capacitor Semiconductor memory device with a decoupling capacitor

2006-02-21

2006-02-21

Yoha, Connie C. (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S182000, C365S183000, C365S230080, C365S206000

Reexamination Certificate

active

07002872

ABSTRACT:
A semiconductor memory device includes a core block having sub-arrays and sense amplifier regions. First and second charge storing regions are disposed at sides of the core block. First and second decoupling capacitors are formed at the first and second charge storing regions, respectively. A plurality of first voltage supply lines are disposed to supply a power supply voltage to the sense amplifier regions and are connected to one electrode of each of the first and second decoupling capacitors. A plurality of second voltage supply lines are disposed to supply a ground voltage to the sense amplifier regions and are connected to the other electrode of each of the first and second decoupling capacitors.

REFERENCES:
patent: 4980799 (1990-12-01), Tobita
patent: 5030859 (1991-07-01), Ihara
patent: 5173875 (1992-12-01), Komatsu et al.
patent: 6160747 (2000-12-01), Brox et al.
patent: 6337823 (2002-01-01), Seo et al.
patent: 10-0268745 (2000-10-01), None

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