Semiconductor memory device with a data clear circuit

Details Semiconductor memory device with a data clear circuit Semiconductor memory device with a data clear circuit

1988-03-03

1989-11-07

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

36518908, 365218, G11C 700, G11C 1140

Patent

active

048796867

ABSTRACT:
A semiconductor memory device comprising a memory cell-selecting section, an input supply control section, and a bit-line potential control section. The memory cell-selecting section includes a row decoder and a first gate circuit coupled to the output thereof. The memory cell-selecting section drives all the memory cells making up the memory device, when it is set in the mode for clearing the memory device, and the input data supply control section disconnects a pair of bit lines from a write circuit when the control section is set in this same mode. When the bit-line potential control section is set in the memory-clearing mode, it sets the potential of one of the bit lines at a high level, and the potential of the other bit line at a low potential.

REFERENCES:
patent: 4272834 (1981-06-01), Noguchi et al.
patent: 4393473 (1983-07-01), Rufford
patent: 4481610 (1984-11-01), Takemae et al.
patent: 4516224 (1985-05-01), Aoyama
patent: 4766571 (1988-08-01), Kawashima
patent: 4780847 (1988-10-01), Ito

Affiliated with

Also associated with

Rating

Semiconductor memory device with a data clear circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device with a data clear circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device with a data clear circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-87290