Semiconductor memory device with a concentrated impurities in ch

Details Semiconductor memory device with a concentrated impurities in ch Semiconductor memory device with a concentrated impurities in ch

1997-05-09

1999-07-13

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257335, 257337, 257338, 257339, 257345, 257368, H01L 2972

Patent

active

059230649

ABSTRACT:
A semiconductor memory device is provided which includes: a memory cell portion including at least one gate electrode formed on a semiconductor substrate and a plurality of source/drain regions formed in the semiconductor substrate and extending parallel to each other and perpendicular to the gate electrode, the gate electrode and the plurality of source/drain regions constituting a plurality of first conductivity type channel transistors; and a peripheral circuitry portion including a first conductivity type channel transistor having a gate electrode formed on the semiconductor substrate and source/drain regions; wherein channels of the first conductivity type channel transistors in the memory cell portion each have a higher impurity concentration than a channel of the first conductivity type channel transistor in the peripheral circuitry portion.

REFERENCES:
patent: 5348904 (1994-09-01), Koyama
patent: 5359221 (1994-10-01), Miyamoto et al.
patent: 5406521 (1995-04-01), Hara
patent: 5422505 (1995-06-01), Shirai
patent: 5449937 (1995-09-01), Arimura et al.
patent: 5592421 (1997-01-01), Kaneko et al.
Okumura et al., "Source-to-Drain Nonuniformly Doped Channel (NUDC) MOSFET Structures for High Current Drivability and Threshold Voltage Controllability," IEEE Transactions on Electron Devices, vol. 39, No. 11, pp. 2541-2552, Nov. 1992.

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