Semiconductor memory device with a built-in test circuit

Static information storage and retrieval – Read/write circuit – Testing

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G11C 2900

Patent

active

048978175

ABSTRACT:
A semiconductor memory device provided with an on-chip test circuit is disclosed. The on-chip test circuit includes a test write circuit for writing the same write data to at least two memory cells, simultaneously in a test mode, a selection circuit for simultaneously reading stored data from the above at least two memory cells and a comparison circuit for comparing data read from the at least two memory cells whose comparison output shows whether at least one of the at least two memory cells is bad, or all of the at least two memory cells are good.

REFERENCES:
patent: 4337522 (1982-06-01), Stewart
patent: 4744061 (1988-05-01), Takemae

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