Semiconductor memory device which controls refresh of a...

Details Semiconductor memory device which controls refresh of a... Semiconductor memory device which controls refresh of a...

2007-04-17

2008-12-30

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S236000, C365S239000

Reexamination Certificate

active

07471586

ABSTRACT:
A semiconductor memory device is comprised of a refresh counter for sequentially generating a count value indicating one or more row addresses corresponding to one or more word lines to be refreshed when receiving a refresh request at a predetermined interval in normal operation, in which the refresh counter includes n+1 stage counters assigned to n bits included in the row address and a dummy bit not included in the row address, and a counter portion from the least significant bit to the dummy bit forms an N-ary counter, so as to control whether or not refresh is performed in response to a value of the dummy bit when receiving the refresh request.

REFERENCES:
patent: 6449204 (2002-09-01), Arimoto et al.
patent: 6721223 (2004-04-01), Matsumoto et al.
patent: 6807121 (2004-10-01), Natsui et al.
patent: 6876592 (2005-04-01), Takahashi et al.
patent: 7317650 (2008-01-01), Shinozaki et al.
patent: 2003-187578 (2003-07-01), None

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