Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2005-08-16
2005-08-16
Yoha, Connie C. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S230010, C365S230020, C365S230030
Reexamination Certificate
active
06930933
ABSTRACT:
Redundancy circuits for accessing the stored data in the memory banks are provided in a semiconductor memory. First and second memory banks, each has 2N number of redundancy lines. Only N number of redundancy lines in each memory bank is utilized during normal operations. During normal operations, a first redundancy control block provides N number of redundancy signals to the first memory bank. A second redundancy control block provides N number of redundancy signals to the second memory bank. An address signal switching unit receives memory bank failure signals. During normal operations, the address signal switching unit multiplexes the N number of redundancy signals from the redundancy control block to the N number of redundancy lines of the corresponding memory bank. Upon failure of a memory bank, the address signal switching unit multiplexes the N number of the redundancy signals corresponding to the failed memory bank to the other operational memory bank so that the operational memory bank utilize a total of 2N number of redundancy lines.
REFERENCES:
patent: 5495447 (1996-02-01), Butler et al.
patent: 5548553 (1996-08-01), Cooper et al.
patent: 6021512 (2000-02-01), Lattimore et al.
Hynix / Semiconductor Inc.
Ladas & Parry LLP
Yoha Connie C.
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