Semiconductor memory device which can be tested while selecting

Static information storage and retrieval – Read/write circuit – Data refresh

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365233, G11C 700

Patent

active

059432802

ABSTRACT:
When a special operation mode is instructed, a test oscillation circuit operating at a cycle shorter than a refresh oscillation circuit specifying the cycle of self refresh is activated according to an external row address strobe signal. The internal row address strobe signal is provided to row related control circuitry via a selector. An internal row address strobe signal can be rendered active at a cycle shorter than the cycle of the external row address strobe signal, to carry out row selection. A row is selected at a cycle shorter than the transition cycle of an external signal.

REFERENCES:
patent: 4985868 (1991-01-01), Nakano et al.
patent: 5717652 (1998-02-01), Ooishi
patent: 5751655 (1998-05-01), Yamazaki et al.
patent: 5805508 (1998-09-01), Tobita

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