Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2001-07-23
2002-10-29
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S230060
Reexamination Certificate
active
06473345
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices which can be simultaneously tested even when the number of them is large and a semiconductor wafer on which the semiconductor memory devices are formed.
2. Description of the Background Art
A semiconductor memory device (also called a “semiconductor memory chip”) on which memory cells for inputting/outputting data are arranged in a matrix is subjected to processes shown in FIG.
22
and then shipped. Specifically, referring to
FIG. 22
, a wafer process for forming a number of semiconductor memory chips on a semiconductor wafer such as a silicon (Si) wafer by an LSI process is performed (step S
1
). At a stage when the wafer process is finished, as shown in
FIG. 23
, a semiconductor wafer
700
has device areas
701
on which the semiconductor memory chips are formed and areas
702
on which no semiconductor memory chip is formed. The device areas
701
are arranged in a grid pattern.
An operation test for each of the semiconductor memory chips is conducted on the semiconductor wafer on which the semiconductor memory chips are formed as shown in
FIG. 23
(step S
2
). After that, semiconductor memory chips determined as non-defective by the operation test are separated by cutting the semiconductor wafer
700
along the areas
702
in which no semiconductor memory chip, and an assembling process of packaging the chips is carried out (step S
3
). In a packaged state, an operation test is conducted again on each of the semiconductor memory chips (step S
4
), and only the semiconductor memory chips which passed the operation test are shipped.
The operation tests in step S
2
and S
4
are, as shown in
FIG. 24
, a writing test (step S
5
) for writing data into each of the memory cells and a reading test (step S
6
) for reading the written data and confirming that the read data coincides with the written data.
The operation test on each of the semiconductor memory chips is carried out by, as shown in
FIG. 25
, connecting a plurality of semiconductor memory chips to a tester. A tester
800
has a signal generating circuit
801
, an address generating circuit
803
, data generating circuits
805
,
809
,
813
, and
817
, determining circuits
807
,
811
,
815
, and
819
, drivers
802
,
804
,
806
,
810
,
814
, and
818
, and comparators
808
,
812
,
816
, and
820
. The signal generating circuit
801
generates a chip enable signal /CE for activating semiconductor memory chips
901
to
904
. The driver
802
converts the chip enable signal /CE generated by the signal generating circuit
801
to a voltage value indicative of the H (logical high) level or the L (logical low) level and outputs the voltage value to the semiconductor memory chips
901
to
904
. The address generating circuit
803
generates an address for designating one of memory cells (not shown) arranged in a matrix in each of the semiconductor memory chips
901
to
904
. The driver
804
converts the address generated by the address generating circuit
803
into a voltage value indicative of the address and outputs the voltage value to the semiconductor memory chips
901
to
904
.
The data generating circuits
805
,
809
,
813
, and
817
generate data to be written into the semiconductor memory chips
901
to
904
at the time of the writing test in the operation test. Each of the drivers
806
,
810
,
814
, and
818
converts the data generated by the data generating circuits
805
,
809
,
813
, and
817
into a voltage value indicative of “1” or “0” and outputs the voltage value to the semiconductor memory chips
901
to
904
, respectively.
Each of the comparators
808
,
812
,
816
, and
820
compares data read from the semiconductor memory chips
901
to
904
with a predetermined level at the time of the reading test in the operation test and converts the data to the logical value “1” or “0”. Each of the determining circuits
807
,
811
,
815
, and
819
compares data supplied from the comparators
808
,
812
,
816
, and
820
with data generated at the time of the writing test by the data generating circuits
805
,
809
,
813
, and
817
and determines whether the read data coincides with the write data or not.
The semiconductor memory chip
901
has a control terminal
905
, an address terminal
906
, and a data terminal
907
. The semiconductor memory chip
902
has a control terminal
908
, an address terminal
909
, and a data terminal
910
. The semiconductor memory chip
903
has a control terminal
911
, an address terminal
912
, and a data terminal
913
. The semiconductor memory chip
904
has a control terminal
914
, an address terminal
915
, and a data terminal
916
. The control terminals
905
,
908
,
911
, and
914
are terminals for supplying the chip enable signal /CE to the semiconductor memory chips
901
to
904
, respectively. The address terminals
906
,
909
,
912
, and
915
are terminals for supplying an address to the semiconductor memory chips
901
to
904
, respectively. The data terminals
907
,
910
,
913
, and
916
are terminals for inputting/outputting data from/to the semiconductor memory chips
901
to
904
, respectively.
In
FIG. 25
, although not shown in detail, each of the address terminals
906
,
909
,
912
, and
915
is comprised of
22
terminals, and each of the data terminals
907
,
910
,
913
, and
916
is comprised of 16 terminals.
FIG. 25
shows a case where the operation test is conducted simultaneously on the four semiconductor memory chips
901
to
904
.
Each of the semiconductor memory chips
901
to
904
has an activating/inactivating circuit
920
shown in FIG.
26
. Referring to
FIG. 26
, the activating/inactivating circuit
920
has inverters
921
to
923
. The chip enable signal /CE outputted from the driver
802
of the tester
800
is supplied via each of the control terminals
905
,
908
,
911
, and
914
of the semiconductor memory chips
901
to
904
to the activating/inactivating circuit
920
. The activating/inactivating circuit
920
inverts the logic of the supplied chip enable signal /CE three times, that is, inverts the logic of the supplied chip enable signal /CE and outputs the inverted logic. When the chip enable signal /CE of the L level is entered, the activating/inactivating circuit
920
therefore outputs a signal of the H level to activate the semiconductor memory chips
901
to
904
. When the chip enable signal /CE of the H level is entered, the activating/inactivating circuit
920
outputs a signal of the L level to make the semiconductor memory chips
901
to
904
inactive.
Referring to
FIGS. 25 and 27
, an operation of conducting an operation test simultaneously on the semiconductor memory chips
901
to
904
will be described. In a period T
1
, data is written to the semiconductor memory chips
901
to
904
. In a period T
2
, data is read from the semiconductor memory chips
901
to
904
.
In the period T
1
, the signal generating circuit
801
in the tester
800
generates the chip enable signal /CE of the L level, and the driver
802
converts the signal to a voltage value indicative of the chip enable signal /CE of the L level and outputs the voltage value. The chip enable signal /CE of the L level is supplied to the semiconductor memory chips
901
to
904
via the control terminals
905
,
908
,
911
, and
914
to activate each of the semiconductor memory chips
901
to
904
. After that, a write enable signal /WE is generated by a signal generating circuit (not shown) and supplied from a control terminal (not shown) to make the semiconductor memory chips
901
to
904
enter a data writable state.
The address generating circuit
803
generates an address “Address” to designate one of the memory cells arranged in the matrix in each of the semiconductor memory chips
901
to
904
, and the driver
804
converts the generated address “Address” to a voltage value and outputs the voltage value. The address “Address” outputted from the tester
800
is supplied via the addre
Hayasaka Takashi
Miyawaki Yoshikazu
Ohba Atsushi
LandOfFree
SEMICONDUCTOR MEMORY DEVICE WHICH CAN BE SIMULTANEOUSLY... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with SEMICONDUCTOR MEMORY DEVICE WHICH CAN BE SIMULTANEOUSLY..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and SEMICONDUCTOR MEMORY DEVICE WHICH CAN BE SIMULTANEOUSLY... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2997102