Semiconductor memory device utilizing multiple edges of a...

Details Semiconductor memory device utilizing multiple edges of a... Semiconductor memory device utilizing multiple edges of a...

2000-05-16

2001-06-26

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S189050, C365S233100

Reexamination Certificate

active

06252812

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly to a DDR-SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory).
2. Description of Related Art
In recent years, performance of the CPU has been noticeably improved. If, however, no matter how fast an operating speed of the CPU may be increased, a data transfer rate of a DRAM to be used as its main memory does not catch up with it, the CPU will not be able to exhibit its performance. For this reason, improvement in the data transfer rate of the DRAM has been strongly requested in recent years, and as one meeting this request, SDRAM (Synchronous Dynamic Random Access Memory) has been already developed.
The SDRAM is a memory capable of continuously reading out, upon receipt of a clock signal from outside of the chip, each data stored in continuous addresses in synchronism with the clock signal, and the interior thereof is rendered as pipelines to make the operation fast.
However, the frequency of a clock signal to be used for the SDRAM is not higher than about 100 MHz, but is still low as compared with the operating frequency of the CPU. On the other hand, it is difficult in view of the circuit characteristics within the DRAM to further increase the frequency of the clock signal.
In order to solve this problem, a DDR-SDRAM has been proposed and put into practical use in which both leading edge and trailing edge of the clock signal are used. The DDR-SDRAM uses both edges of the clock signal, and therefore, is capable of performing the same high-rate data transfer as the frequency of the clock signal redoubled equivalently.
FIG. 8
is a view showing a conventional input/latch circuit
100
in the DDR-SDRAM. The input/latch circuit
100
shown in
FIG. 8
is provided with a flip flop
104
for holding write data supplied to a data input/output terminal DQ at a leading edge of a timing signal DQS; a flip flop
106
for holding at its trailing edge; a flip flop
108
for holding output
114
from the flip flop
104
in response to a leading edge of an inversion clock signal CLKB; and a flip flop
110
and a flip flop
112
for holding output
116
from the flip flop
108
and output
118
from the flip flop
106
respectively in response to the leading edge of the clock signal CLK. In this respect, an initial-stage circuit
102
is a circuit to convert amplitude of write data to be supplied to the data input/output terminal DQ into amplitude to be used within the chip.
FIG. 9
shows an operation of the input/latch circuit
100
. In this respect, as shown in
FIG. 9
, an inversion clock signal CLKB is a signal obtained by inverting the phase of the clock signal CLK, and a timing signal DQS is a timing signal in synchronism with the clock signal CLK.
As shown in
FIG. 9
, write data to be supplied to the data input/output terminal DQ varies in a period equal to half the period of the clock signal CLK, and these write data are held by the flip flop
104
in response to the leading edge of the timing signal DQS, and are held by the flip flop
106
in response to the trailing edge of the timing signal DQS. A signal held by the flip flop
104
is indicated as output
114
, and a signal held by the flip flop
106
is indicated as output
118
. Of these, the output
116
is held by the flip flop
108
in response to the leading edge of the inversion clock signal CLKB, and its output is indicated as
116
.
These output
116
and
118
are held by the flip flops
110
and
112
respectively in response to the leading edge of the clock signal CLK, and their output becomes Drise and Dfall respectively.
These Drise and Dfall are written in parallel in a memory cell via a data write circuit (not shown).
As described above, in the input/latch circuit
100
, write data to be supplied to the data input/output terminal DQ are latched using both a leading edge and a trailing edge of the timing signal DQS, and these write data thus latched are arranged in parallel within. Therefore, apparently, it looks as if the operation was performed in a frequency twice as high as that of the clock signal CLK. If the frequency of the clock signal CLK is, for example, 100 MHz, the frequency of the write data will become 200 MHz. In this case, it can be seen that the interior of the DDR-SDRAM is operating firmly at 100 MHz and the data transfer rate is increased without raising the operating frequency within the chip.
As described above, the DDR-SDRAM captures write data by taking advantage of both edges of the timing signal DQS using the timing signal DQS and the inversion clock signal CLKB, and arranges the write data in parallel within, and therefore, the high-rate data transfer is realized. For this reason, even in various tests of the DDR-SDRAM to be conducted before shipment, it is necessary to supply the timing signal DQS and the inversion clock signal CLKB to the chip, but the timing signal DQS and the inversion clock signal CLKB are signals which are not normally used in the SDRAM. For this reason, a test apparatus, which has been used in the normal SDRAM test in which the timing signal DQS and the inversion clock signal CLKB are not used, cannot be used for the test for the DDR-SDRAM as it is, but the need for a test apparatus exclusively used for the DDR-SDRAM arises.
Among various tests to be conducted before shipment, however, there are also included a multiplicity of tests which have not to be conducted while being operated at high speed, such as, for example, a bar-in test (acceleration test) and if the test apparatus exclusively used for the DDR-SDRAM has to be used for such tests, the cost would be increased to raise the unit price of the chip.
SUMMARY OF THE INVENTION
Therefore, it is an object according to the present invention to provide a semiconductor memory capable of conducting, at low cost, various tests to be conducted before shipment.
According to the present invention, there is provided a semiconductor memory comprising: a first flip flop circuit for holding, in response to a clock signal, write data fetched in response to one edge of a timing signal; a second flip flop circuit for holding, in response to the clock signal, write data fetched in response to the other edge of the timing signal; a write circuit for writing write data held by the first and second flip flop circuits on memory cell array in parallel, characterized by having means for storing common write data in the first and second flip flop circuits in response to the clock signal independently of the timing signal during a test.
Also, there is provided a semiconductor memory further comprising: a third flip flop circuit for holding write data in response to the one edge of the timing signal; and a fourth flip flop circuit for holding write data in response to the other edge of the timing signal, characterized in that the means supplies write data held by the third and fourth flip flop circuits to the first and second flip flop circuits respectively during a normal operation, and commonly supplies write data to the first and second flip flops while write data held by the third and fourth flip flop circuits are inhibited from being supplied to the first and second flip flop circuits respectively during the test.
Further, the write circuit is characterized by comprising: a first amplifier for writing write data held by the first flip flop circuit on the memory cell array; a second amplifier for writing write data held by the second flip flop circuit on the memory cell array; and inhibit means for inhibiting an operation of either of the first and second amplifiers during the test.
Further, the inhibition means is also characterized by determining the operation of which of the amplifiers should be inhibited based on part of an address signal.
Further, it is characterized in that the part of the address signal is a specific bit of a column address, and that in the memory cell array, two memory cells being different from each other only in the specific bit of the column address are arranged

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