Semiconductor memory device using row redundancy and I/O...

Details Semiconductor memory device using row redundancy and I/O... Semiconductor memory device using row redundancy and I/O...

2007-11-20

2007-11-20

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000, C365S225700, C365S189070, C365S189050, C365S236000, C365S230020, C714S711000, C714S710000

Reexamination Certificate

active

11408995

ABSTRACT:
To reduce the area relating to location of redundant elements for relieving defects of a memory. A memory device has row address and input/output data as two dimensional redundancy parameters for relieving defects of an embedded memory30. It comprises a built-in self-test circuit10for testing defects of the embedded memory30, a redundant element location operator20for determining which redundant element replaces a defect based on a preset order and according to the order in which defects are detected by the self-test circuit10, and a row redundancy unit31and an I/O redundancy unit32for replacing the defects in the embedded memory according to the determined order. The redundant element location operator20determines the priority axis according to the preset order and according to the order in which the defects are detected, and holds redundant element location information.

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