Semiconductor memory device using pipelined-buffer...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185050, C365S189050

Reexamination Certificate

active

07599222

ABSTRACT:
Disclosed is a semiconductor memory device which is operable a pipelined-buffer programming and includes a cell array including a plurality of memory cells, a write driver circuit divided into a plurality of write units, each write unit programming memory cells with a first data, a sense amplifier circuit divided into plurality of read units of the same number as the plurality of write units, each read unit sensing bit lines of the cell array during a program verify operation, a selection circuit for selecting one of the write units and one of the read units in response to a column address and a data input circuit for providing the first data to the selected write unit during a program operation and for receiving verifying data from the selected read unit during the program verify operation.

REFERENCES:
patent: 6259628 (2001-07-01), Park
patent: 6421274 (2002-07-01), Yoshimura
patent: 6625063 (2003-09-01), Kim
patent: 6697287 (2004-02-01), Furukawa
patent: 6842377 (2005-01-01), Takano et al.
patent: 2005/0237820 (2005-10-01), Takemura et al.
patent: 2002-288034 (2002-10-01), None
patent: 2003-216483 (2003-07-01), None
patent: 2003-308698 (2003-10-01), None

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