Semiconductor memory device using ferroelectric film

Details Semiconductor memory device using ferroelectric film Semiconductor memory device using ferroelectric film

2001-06-13

2002-04-02

Mai, Son (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S230030

Reexamination Certificate

active

06366490

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-251853, filed Aug. 23, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor memory device using a ferroelectric film. More particularly, this invention relates to a series-connected TC parallel-unit type ferroelectric RAM (Random Access Memory) composed of a series connection of a plurality of unit cells, each unit cell being such that a ferroelectric capacitor (C) is connected between the source and drain of a cell transistor (T).
It is common knowledge that ferroelectric memories are nonvolatile, like flash memories, and have the ability to effect high-speed access and high-speed rewriting, like DRAMs. Furthermore, the ferroelectric memory is capable of operating on a lower voltage and consuming less power than the flash memory. That is, although being a nonvolatile device, the ferroelectric memory has the advantages of achieving a larger number of rewrites and a shorter write time and being capable of operating on a lower voltage and consuming less power.
The cell structure of the ferroelectric memory has been generally developed using a one-transistor one-capacitor cell.
In a conventional ferroelectric memory of
FIG. 9
, a plurality of memory cells MCs are placed at the intersections of word lines WLs and pair of bit lines (bit line pairs) BLs, BBLs complementary to each other, the word lines crossing at right angles with the bit line pairs, in such a manner that they are located at every other intersection. A plate electrode wire PL is placed in parallel with each of the word lines WL. Each of the plate electrode wires PLs and each of the word lines WLs are controlled by a row decoder/plate electrode wire driving circuit (RD & PD)
105
controlled according to row addresses.
Each of the bit line pairs BLs, BBLs is controlled by a sense amplifier SA controlled according to row addresses. That is, each sense amplifier SA amplifies the data read onto a pair of bit lines BL, BBL.
The read or write data is inputted or outputted via a pair of data lines (data line pair) DQ, BDQ complementary to each other.
The row decoder/plate electrode wire driving circuit
105
is controlled by a row control circuit
109
.
The row decoder circuit
109
is controlled on the basis of a chip enable signal CEB transmitted over a chip enable signal wire
110
and a row address signal Adr transmitted over a row address signal wire
120
.
A column decoder (CD)
115
is controlled on the basis of the output of a column control circuit
114
. The column control circuit
114
is controlled on the basis of the chip enable signal CEB and a column address signal Adc transmitted over a column address signal wire
121
.
A read/write control circuit
119
is controlled by the chip enable signal CEB and a read/write signal RW transmitted over read/write signal wires
111
. A read data latch
113
and a write data latch
116
are controlled by the read/write control circuit
119
. The read data latch
113
and write data latch
116
are connected to the pair of data lines DQ, BDQ, respectively. The read data latch
113
outputs an output signal (read data) Dout. An input signal (write data) Din is inputted to the write data latch
116
.
FIG. 10
shows, in further detail, the circuit configuration of the part indicated by A or FIG.
9
.
In
FIG. 10
, for example, four memory cells MCs are placed between bit lines BL
0
, BBL
0
making a pair. Specifically, the gate of a first cell transistor M
0
is connected to word line WL
0
. One electrode of a first cell capacitor C
0
is connected to plate electrode wire PL
0
and the other electrode of the first cell capacitor C
0
is connected to one of the source and drain of the first cell transistor M
0
. The other of the source and drain of the first cell transistor M
0
is connected to bit line BL
0
.
The gate of a second cell transistor M
1
is connected to word line WL
1
. One of the source and drain of the second cell transistor M
1
is connected to bit line BL
0
. One electrode of a second cell capacitor C
1
is connected to plate electrode wire PL
1
and the other electrode of the second cell capacitor C
1
is connected to the other of the source and drain of the second cell transistor M
1
.
The gate of a third cell transistor M
2
is connected to word line WL
2
. One electrode of a third cell capacitor C
2
is connected to plate electrode wire PL
2
and the other electrode of the third cell capacitor C
2
is connected to one of the source and drain of the third cell transistor M
2
. The other of the source and drain of the third cell transistor M
2
is connected to bit line BBL
0
.
The gate of a fourth cell transistor M
3
is connected to word line WL
3
. One of the source and drain of the fourth cell transistor M
3
is connected to bit line BBL
0
. One electrode of a fourth cell capacitor C
3
is connected to plate electrode wire PL
3
and the other electrode of the fourth cell capacitor C
3
is connected to the other of the source and drain of the fourth cell transistor M
3
.
With this configuration, the plate electrode wires PL
0
, PL
1
, PL
2
, PL
3
are provided for the cell capacitors C
0
, C
1
, C
2
, C
3
, respectively. The plate electrode wires PL
0
, PL
1
, PL
2
, PL
3
are provided in the longitudinal direction of the word lines WL
0
, WL
1
, WL
2
, WL
3
, respectively.
In this connection, a ferroelectric memory with one-transistor one-capacity cells where the plate electrode wires are provided in the longitudinal direction of bit lines has been disclosed in U.S. Pat. No. 5,400,275 (Jpn. Pat. Appln. KOKAI Publication No. 4-42498). In the ferroelectric memory, for example, four memory cells MCs, as shown in
FIG. 11
, are placed between bit lines BL
0
, BBL
0
making a pair.
Specifically, the gate of a first cell transistor M
0
is connected to word line WL
0
. One electrode of a first cell capacitor C
0
is connected to plate electrode wire PL
0
and the other electrode of the first cell capacitor C
0
is connected to one of the source and drain of a first cell transistor M
0
. The other of the source and drain of the first cell transistor M
0
is connected to bit line BL
0
.
The gate of a second cell transistor M
1
is connected to word line WL
1
. One of the source and drain of the second cell transistor M
1
is connected to bit line BL
0
. One electrode of a second cell capacitor C
1
is connected to plate electrode wire PL
0
and the other electrode of the second cell capacitor C
1
is connected to the other of the source and drain of the second cell transistor M
1
.
The gate of a third cell transistor M
2
is connected to word line WL
2
. One electrode of a third cell capacitor C
2
is connected to plate electrode wire PL
0
and the other electrode of the third cell capacitor C
2
is connected to one of the source and drain of a third cell transistor M
2
. The other of the source and drain of the third cell transistor M
2
is connected to bit line BBL
0
.
The gate of a fourth cell transistor M
3
is connected to word line WL
3
. One of the source and drain of the fourth cell transistor M
3
is connected to bit line BBL
0
. One electrode of a fourth cell capacitor C
3
is connected to plate electrode wire PL
0
and the other electrode of the fourth cell capacitor C
3
is connected to the other of the source and drain of the fourth cell transistor M
3
.
In this configuration, a single plate electrode wire PL
0
is provided in-parallel with and between bit lines BL
0
, BBL
0
making a pair.
With this configuration, data is read from or written into only the memory cell MC at the intersections of the word lines WL
0
, WL
1
, WL
2
, WL
3
set at the high level and plate electrode wire PL
0
driven to the high level. In this way, by reducing the number of accessed cells, the operating current can be decreased.
Although such a configuration reduces the frequency of access to the memory cells MC and the cur

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