Semiconductor memory device using dynamic data shift...

Details Semiconductor memory device using dynamic data shift... Semiconductor memory device using dynamic data shift...

2008-09-12

2010-12-14

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S189050, C365S230030, C365S230080

Reexamination Certificate

active

07852691

ABSTRACT:
A semiconductor memory device comprises a plurality of submacros mutually connected via global data lines. Each of the submacros includes a first and a second memory block, and a memory block control circuit arranged between the first and second memory blocks. The memory block control circuit includes a DQ buffer block connected to the first memory block via first complementary data lines and connected to the second memory block via second complementary data lines. It also includes a dynamic data shift redundancy circuit block connected to the DQ buffer block via local data lines and operative to relieve the first and second memory blocks.

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