Semiconductor memory device that requires refresh operations

Details Semiconductor memory device that requires refresh operations Semiconductor memory device that requires refresh operations

2007-05-08

2007-05-08

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S195000, C365S236000

Reexamination Certificate

active

11347293

ABSTRACT:
A semiconductor memory device includes a refresh counter that outputs an address of a word line to be refreshed, a ROM circuit that stores a relevant address related to a refresh defective address, and a multiple refresh control circuit that simultaneously or continuously activates the refresh defective address and the relevant address within one refresh cycle in response to a fact that the ROM circuit detects the relevant address. The multiple refresh control circuit excludes a pattern having a risk that a power supply potential or a ground potential varies greatly such as a pattern that the multiple refresh occurs continuously. With this arrangement, a refresh defective cell can be saved while restricting the variation in the power supply potential or the ground potential.

REFERENCES:
patent: 5559748 (1996-09-01), Numata et al.
patent: 6141288 (2000-10-01), Numata et al.
patent: 6487135 (2002-11-01), Watanabe et al.
patent: 2000-132963 (2000-05-01), None

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