Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2011-04-05
2011-04-05
Sefer, A. (Department: 2893)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S261000, C438S294000, C257SE29018, C257SE21540
Reexamination Certificate
active
07919389
ABSTRACT:
A semiconductor memory device having a memory cell region and a peripheral circuit region, and a method of manufacturing such a semiconductor memory device, are proposed, in which trench grooves are formed to be shallow in the memory cell region in order to improve the yield, and trench grooves are formed to be deep in the high voltage transistor region of the peripheral circuit region, in particular in a high voltage transistor region thereof, in order to improve the element isolation withstand voltage. A plurality of memory cell transistors having an ONO layer15serving as a charge accumulating insulating layer are provided in the memory cell region, where element isolation grooves6for these memory cell transistors are narrow and shallow. Two types of transistors, one for high voltage and the other for low voltage, having gate insulating layers16or17, which are different from the ONO layer15in the memory cell region, are provided in the peripheral circuit region, where at least element isolation grooves23for high voltage transistors are wide and deep. In this way, it is possible to improve the degree of integration and yield in the memory cell region, and secure withstand voltage in the peripheral circuit region.
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Goda Akira
Noguchi Mitsuhiro
Kabushiki Kaisha Toshiba
Nguyen Dilinh P
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
Sefer A.
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