Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2011-08-02
2011-08-02
Dinh, Son T (Department: 2824)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S230030, C365S233100
Reexamination Certificate
active
07990799
ABSTRACT:
Example embodiments relate to a semiconductor memory device that includes an address coding method for a multi-word line test, for example, an address coding method to test a semiconductor memory device having a cell block row selection circuit. The semiconductor memory device may include a plurality of memory cell blocks, where each memory cell block may include memory cells coupled to a bit line. The method may include coding row addresses of the memory cell block by dividing one or more row addresses corresponding to cell blocks of the memory cell block to create sub-cell blocks and adding the sub-cell blocs into the main cell blocks to create a logical memory block, which enables word lines of the main cell blocks and sub-cell blocks at the same time.
REFERENCES:
patent: 5867440 (1999-02-01), Hidaka
patent: 6256257 (2001-07-01), Park et al.
patent: 7180816 (2007-02-01), Park
patent: 2007/0047367 (2007-03-01), Kim et al.
patent: 10-0535072 (2006-03-01), None
Kim Hyun-Ki
Kwon Whee-jin
Dinh Son T
Harness, Dickey & Pierce P.L.C
Nguyen Nam T
Samsung Electronics Co,. Ltd.
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