Semiconductor memory device that can perform successive...

Details Semiconductor memory device that can perform successive... Semiconductor memory device that can perform successive...

2009-11-06

2011-12-06

Le, Vu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Simultaneous operations

C365S189170, C365S189011, C365S189190, C365S189050

Reexamination Certificate

active

08072821

ABSTRACT:
To provide an input/output circuit that includes a write path to which write data is supplied and a read path to which read data is supplied and first and second data lines that connect the input/output circuit to a memory cell array. The input/output circuit includes a write buffer that supplies the write data on the write path to the first data line, a read amplifier that supplies the read data supplied to the read path through the second data line, and a bypass circuit that supplies the write data on the write path to the read path in response to detection of matching between a write address and a read address. Thus, data collisions can be avoided.

REFERENCES:
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patent: 7603592 (2009-10-01), Sekiguchi et al.
patent: 2004/0037107 (2004-02-01), Matsuoka
patent: 2004-086970 (2004-03-01), None
patent: 2007-042176 (2007-02-01), None
Y. Nakagome et al., “A 1.5V Circuit Technology for 64Mb DRAMs”, Symposium on VLSI Circuits, Dig of Tech. Papers, 1990, pp. 17-18.
Kiyoo Itoh, “Super LSI Memory”, ISBN4563036099, published by Baihukan, Nov. 1994, pp. 165-167.

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