Semiconductor memory device tester

Details Semiconductor memory device tester Semiconductor memory device tester

2001-08-02

2002-03-26

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

Reexamination Certificate

active

06363022

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device tester for testing memory devices of the type that do data input and output in packet format.
With a view to avoiding an increase in the number of address pins by increased memory capacity, RDRAM-type memory devices are now widely used in which a packet signal containing address data, write data, control signal data and so forth is applied as parallel data to a smaller number of pins than the number of digits of the memory address over a plurality of cycles and in the memory device the address data, the control signal data and so forth are reconstructed from the parallel data. In testing the memory device of this type, too, pattern data containing address data, write data and control signal data for test use is converted to a packet signal for application as parallel data to a plurality of pins of the memory device over a plurality of cycles.
In
FIG. 4
there is illustrated in block form the general construction of a conventional semiconductor device tester for testing semiconductor memory devices which perform input and output of data in packet form. The
FIG. 4
configuration is shown to include a minimum number of constituent elements necessary to describe the present invention. That is, a typical IC tester comprises a pattern generator
11
, a programmable data select part
12
and a logic comparison part
14
. The programmable data select part
12
is made up of a plurality of channels
15
A to
15
H corresponding to pins of a memory device under test (hereinafter referred to as a DUT)
13
, respectively. The channel
15
A comprises a packet generating part
12
A, a data setting part
121
-A and a data selection control part
122
-A, and each of the other channels
15
B to
15
H is also similarly constructed.
The pattern generator
11
generates, for example, 65-bit parallel pattern data X
0
to X
15
, Y
0
to Y
15
, C
0
to C
16
and MD
0
to MD
15
as shown in
FIG. 5A and a
parallel 4-bit packet select signal CYP=(CYP
0
, . . . , CYP
3
) that changes at every cycle. These 65-bit parallel pattern data and 4-bit parallel packet select signal are provided to all the channels
15
A to
15
H in common to them. The bit positions of the 65 bits of the parallel pattern data are defined by, for instance, numbers 0 to 64. The packet generating parts
12
A to
12
H in the channels
15
A to
15
H each appropriately select and output a data bit in the 65-bit pattern data at a specified bit position. As a result of this, the pattern data X
0
to X
15
, Y
0
to Y
15
, C
0
to C
16
and MD
0
to MD
15
are rearranged by the channels
15
A to
15
H on the time axis to form an 8-channel packet signal. The packet signal thus obtained is input to the DUT
13
.
Output data (provided in packet format) OT from the DUT
13
is provided to the logic comparison part
14
, wherein it is compared with expected value data EV output in packet form from the programmable data select part
12
to determine whether the DUT
13
is defective or nondefective, and the logic comparison part
14
gives pass/fail results P/F.
Now, a description will be given of the format that is defined by the DUT
13
for the packet signal applied to its input terminal and the format of the packet signal that is generated from the pattern data fed from the pattern generator
11
in accordance with the format defined by the DUT
13
.
FIG. 5B
depicts a row-address packet signal format PG
1
that is defined by the DUT
13
for a packet signal provided as pin data DA, DB and DC to three row address pins A, B and C of the DUT
13
.
FIG. 6A
depicts a column-address packet signal format PG
3
that is defined by the DUT
13
for a packet signal provided as pin data DD, DE, DF, DG and DH to five column address pin D, E, F, G and H of the DUT
13
.
As depicted in
FIG. 5B
, the row-address packet signal format PG
1
defined by the DUT
13
has a parallel 3-bit, 8-cycle configuration, which includes a 3-by-3 bit area CTLA for control signal, a 3-by-2 bit area BAA for bank address signal, a 3-by-3 bit area RAA for row address signal, and a 3-bit area RCA for recognition signal inserted between the bank address signal area BAA and the row address signal area RAA. In these areas CTLA, BAA, RCA and RAA there are sequentially allocated on a bitwise basis control signal bits DR
4
T, DR
4
F and DR
3
to DR
0
, bank address bits BR
0
to BR
4
, a recognition signal bit AV and row-address signal bits R
8
to R
0
. Accordingly, the bank address signal area BAA has a 1-bit blank, and the recognition signal area RCA has a 2-bit blank. For these three blanks of bits and a recognition signal bit AV, data are produced by the packet generating parts
12
A,
12
B and
12
C rather than by the pattern generator
11
. The parallel 3-bit data thus produced is provided to the three row address pins A, B and C for each cycle following this format PG
1
.
As described above, this example uses, as a control signal indicating the beginning of the packet, the 6-bit data DR
4
T, DR
4
F and DR
3
to DR
0
input to the row address pins A, B and C of the DUT
13
in first and second cycles. Further, 5-bit data BR
0
to BR
4
input to the row-address pins A, B and C in third and fifth cycles is used as a bank address signal for bank specification in the DUT
13
, and 9-bit data R
8
to R
0
input in sixth to eighth cycles is used as a row address signal. The recognition signal AV=1 input to the pin C in a fifth cycle indicates that the 8-cycle input packet signal is a packet signal for row address input use.
FIG. 5C
shows a structure of a packet signal PG
2
generated from the output pattern signal of the pattern generator
11
in accordance with the row-address packet signal format PG
1
of
FIG. 5B
defined by the DUT
13
. Thus, the row-address packet signal defines which of bits of the pattern data X
0
to X
15
, Y
0
to Y
15
, C to C
16
and MD
0
to MD
15
is assigned to which input pin and in which cycle. In this example, the pattern data C
0
to C
5
is assigned to the control signal bits DR
4
T, DR
4
F and DR
3
to DR
0
; the pattern data X
11
to X
15
is assigned to the bank address bits BR
0
to BR
4
; and the pattern data X
0
to X
8
is assigned to the row address signal bits R
0
to R
8
. The blanks in the format PG
1
of
FIG. 5B
are each assigned with “L” logic denoted by FL and the recognition signal bit AV=1 is assigned with “H” logic denoted by FH.
FIG. 6A
shows a packet signal format PG
3
for the column address side. The column-address packet signal has an 8-cycle configuration, as is the case with the row-address packet signal. In a control signal area CTLA, control signal bits DC
4
to DC
0
are assigned to five pins D to H in the first cycle and control signal bits COP
1
, COP
0
and COP
3
are assigned to the pins F, G and H in the second cycle. In a recognition signal area RCA, recognition signal bits S and M are assigned to the pins D and E in the second cycle. In a mask data area MDA, mask data MA
7
to MA
0
are assigned to the pins D and E on a bitwise basis, and the mask data MA
7
to MA
0
are assigned to the pins F, G and H in the third to sixth cycles. In an area RCA at the fifth cycle, the recognition signal bit COP
2
is assigned to the pin H. In a bank address area BAA, a blank and bank address signals BC
4
to BC
0
are assigned to the pins F, G and H in two cycles, and in a column-address area CAA column-address signal bits COL
5
to COL
0
are assigned to the pin E in a seventh cycle and to the pins D to H in the eighth cycle on a bitwise basis. Blanks are assigned to the pin F in the sixth cycle and to the pin D in the seventh cycle.
FIG. 6B
shows a packet signal format PG
4
generated from the pattern data X
0
to X
15
, Y
0
to Y
15
, C
0
to C
16
and MD
0
to MD
15
in accordance with the column-address packet signal format PG
3
depicted in FIG.
6
A. As will be seen from
FIGS. 6A and 6B
, this example shows the case of assigning the pattern data C
6
to C
10
to the control signal bits DC
0
to DC

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