Semiconductor memory device test circuit having an improved comp

Static information storage and retrieval – Read/write circuit – Testing

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36518901, 36518907, 36518908, G11C 700

Patent

active

057779325

ABSTRACT:
A test circuit for a DRAM is disclosed to preform a test operation in a page mode. The test circuit includes a compare control block 7A having a compare determination signal generator circuit 71 which generates a compare determination signal .PHI.1 in response to a change from an active low level to an inactive high level of column address strobe or CAS signal during an active low level of a row address strobe or RAS signal.

REFERENCES:
patent: 5436911 (1995-07-01), Mori
patent: 5557574 (1996-09-01), Senoo et al.
patent: 5559744 (1996-09-01), Kuriyama et al.

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