Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2003-09-05
2004-10-05
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S205000, C365S208000, C365S230030
Reexamination Certificate
active
06801460
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device represented by a memory module having a plurality of memory chips mounted on one board.
2. Description of the Background Art
MOS type semiconductor memory devices, particularly DRAMs (Dynamic Random Access Memory) come to have ever increasing storage capacity along with the development of miniaturization techniques. As the storage capacity of DRAMs increases, there arises stronger demand for higher speed of data processing, that is, demand for data processing of multiple bits in parallel by the memory chip.
In a configuration executing such multiple-bits data processing, it is necessary that a plurality of internal circuits operate in parallel, and as the number of data to be processed increases, current consumption, particularly peak current value becomes excessively large. This results in increased burden on power supply system that drives the circuits, possibly causing a circuit malfunction derived from fluctuation of power supply voltage. Japanese Patent Laying-Open No. 2001-167580 discloses a method of suppressing the peak current as a cause of malfunction, when multiple bits of data are to be processed simultaneously, for example, when two sense amplifiers are to be activated simultaneously at the time of a data read, by shifting the activation timings.
Recently, a memory module has been attracting attention, which realizes larger storage capacity by mounting a plurality of memory chips on one board, along with miniaturization. This is effective in that a large amount of information can be stored and in that multiple bits of data can be processed at high speed as the plurality of memory chips operate independently and in parallel with each other.
In this memory module also, each of the plurality of memory chips operate in parallel simultaneously, and therefore, the peak current of the memory module as a whole increases, as in the case described above.
SUMMARY OF THE INVENTION
The present invention was made to solve the above described problem, and its object is to provide a semiconductor memory device that realizes stable circuit operation without causing any malfunction, by suppressing the peak current.
The semiconductor memory device in accordance with the present invention includes a plurality of memory chips formed on one board, each executing data storage independently, and operating in a parallel. The plurality of memory chips are divided into first and second groups. Each of the memory chips includes a memory array, a precharge circuit, a sense amplifier, a preamplifier, an output buffer, an activation signal generating unit. The memory array has a plurality of memory cells arranged in a matrix of rows and columns, and a plurality of bit lines corresponding to memory cell columns. The precharge circuit is rendered activate before data reading to precharge the bit lines to a-prescribed voltage. The sense amplifier is rendered activate at the time of the data reading to amplify data stored in a plurality of memory cells. The preamplifier is rendered activate at the time of the data reading to further amplify the data that has been amplified by the sense amplifier. The output buffer is rendered activate at the time of the data reading to output the stored data amplified by the preamplifier. The activation signal generating unit generates an activation signal based on a command input for activating at least one of the precharge circuit, the sense amplifier, the preamplifier, and the output buffer. The activation signal generating unit includes a common activation signal generating circuit, a group determination circuit, and a timing control circuit. The common activation signal generating circuit generates a common activation signal based on the command input at the same timing independent of which group each memory chip belongs to. The group determination circuit generates a group determination signal for determining which group the memory chip belongs to. The timing control circuit receives the group determination signal and the common activation signal and generates the activation signal at the timing corresponding to the belonging group of the memory chip.
As described above, in the semiconductor memory device including a plurality of memory chips according to the present invention, the activation signal for activating at least one of the precharge circuit, the sense amplifier, preamplifier, the output buffer is generated at the timing in accordance with a group determining signal determining the belonging group of the memory chip. Accordingly, the maximum value of the peak current that is generated when the these circuits are activated is reduced by half in the entire semiconductor memory device. As the peak current is suppressed, stable operation of the circuits becomes possible.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4912678 (1990-03-01), Mashiko
patent: 4916671 (1990-04-01), Ichiguchi
patent: 5251176 (1993-10-01), Komatsu
patent: 5644773 (1997-07-01), DiMarco
patent: 5999471 (1999-12-01), Choi
patent: 6256244 (2001-07-01), Kim
patent: 63-50998 (1988-03-01), None
patent: P2001-167580 (2001-06-01), None
Mai Son
Renesas Technology Corp.
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