Semiconductor memory device supporting cache and method of drivi

Details Semiconductor memory device supporting cache and method of drivi Semiconductor memory device supporting cache and method of drivi

1991-02-07

1993-07-06

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

365200, 365 49, G11C 1300

Patent

active

052260097

ABSTRACT:
A semiconductor memory device includes a dynamic random access memory (DRAM) cell array (300) as a main memory, a static random access memory (SRAM) cell array (310) as a cache memory, and a content addressable memory (CAM) cell array (320) as a tag memory. The SRAM cell array has word lines (SWL) corresponding in number to match detection lines (23-1 to 23-4) of the CAM cell array. The CAM cell array retrieves contents thereof using external row address as retrieval data. When a match is found in the CAM cell array, a match detection signal is supplied to a match detection line for directly driving a corresponding word line in the SRAM cell array. This semiconductor memory device includes circuitry (22, 22') for generating a cache hit/miss indicating signal in response to signal potentials of the word lines of the SRAM cell array. When the cache hit indicating signal is generated, a column address signal selects a column in the SRAM cell array, and access is made to a memory cell at a crossing between the driven row and selected column of the SRAM cell array. When the cache miss indicating signal is generated, access is made to a memory cell selected by the row address and column address in the DRAM cell array through a column in the SRAM cell array, and in addition data is transferred to a block in the SRAM cell array selected by a block selecting signal from a corresponding block in the DRAM cell array. Further, on a cache miss, data transfer is made prior to external access from a block in the SRAM cell array to a corresponding block in the DRAM cell array.

REFERENCES:
patent: 4740971 (1988-04-01), Tam et al.
patent: 4860262 (1989-08-01), Chiu
patent: 5043943 (1991-08-01), Crisp et al.

Affiliated with

Also associated with

Rating

Semiconductor memory device supporting cache and method of drivi does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device supporting cache and method of drivi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device supporting cache and method of drivi will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1695102